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Volumn 44, Issue 11, 1997, Pages 2070-2077

EXTIGATE: The ultimate process architecture for submicron CMOS technologies

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY;

EID: 0031277336     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.641386     Document Type: Article
Times cited : (16)

References (18)
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    • Bryant, A.1    Haensch, W.2    Mil, T.3
  • 5
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    • "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies,"
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    • P. Sallagoity, M. Ada-Hanifi, M. Paoli, and M. Haond, "Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies," IEEE Electron Devices, vol. 43, p. 1900, Nov. 1996.
    • IEEE Electron Devices
    • Sallagoity, P.1    Ada-Hanifi, M.2    Paoli, M.3    Haond, M.4
  • 6
    • 0030422206 scopus 로고    scopus 로고
    • "Corner rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories," in
    • 1996, p. 833.
    • H. Watanabe, K. Shimizu, Y. Takeuchi, and S. Aritome, "Corner rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories," in IEDM Tech. Dig., 1996, p. 833.
    • IEDM Tech. Dig.
    • Watanabe, H.1    Shimizu, K.2    Takeuchi, Y.3    Aritome, S.4
  • 11
    • 0026385714 scopus 로고    scopus 로고
    • "Technology limitations for n+/p+ polycide gâte CMOS due to lateral dopant diffusion in silicide/polysilicon layers,"
    • vol. 12, p. 696, 1991.
    • C. L. Chu et ai, "Technology limitations for n+/p+ polycide gâte CMOS due to lateral dopant diffusion in silicide/polysilicon layers," IEEE Electron Device Lett., vol. 12, p. 696, 1991.
    • IEEE Electron Device Lett.
    • Chu, C.L.1
  • 12
    • 34648834490 scopus 로고    scopus 로고
    • German Patent no. DE 19535629C1, 1995.
    • U. Schwalke, German Patent no. DE 19535629C1, 1995.
    • Schwalke, U.1
  • 15
  • 16
    • 34648816625 scopus 로고    scopus 로고
    • U.S. Patent 5 164333, 1992.
    • U. Schwalke, U.S. Patent 5 164333, 1992.
    • Schwalke, U.1
  • 17
    • 84920717230 scopus 로고    scopus 로고
    • "Shallow trench isolation for subquarter micron CMOS technologies," in
    • 1996, p. 179.
    • P. Sallagoity, M. Paoli, and M. Haond, "Shallow trench isolation for subquarter micron CMOS technologies," in ESSDERC Conf. Proc., 1996, p. 179.
    • ESSDERC Conf. Proc.
    • Sallagoity, P.1    Paoli, M.2    Haond, M.3
  • 18
    • 0028730614 scopus 로고    scopus 로고
    • "Anomalous narrow channel effect in trench-isolated buried-channel P-MOSFET's,"
    • vol. 15, p. 496, 1994.
    • J. A. Mandelman and J. Alsmeier, "Anomalous narrow channel effect in trench-isolated buried-channel P-MOSFET's," IEEE Electron Device Lett., vol. 15, p. 496, 1994.
    • IEEE Electron Device Lett.
    • Mandelman, J.A.1    Alsmeier, J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.