Technology Limitations for N+/P+ Polycide Gate CMOS Due to Lateral Dopant Diffusion in Silicide/Polysilicon Layers

IEEE Electron Device Letters

Volumn 12, Issue 12, 1991, Pages 696-698

  Chu, Charles L ^a   Chin, Goodwin ^a   Saraswat, Krishna C ^a   Simon Wong, S ^a   Dutton, Robert ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SEMICONDUCTING SILICON--APPLICATIONS; TRANSISTORS--DEGRADATION;

COUPLED 2-D PROCESS; GATE AREA RATIOS; LATERAL DOPANT DIFFUSION; NMOS/PMOS TRANSISTORS; POLYCIDE GATE CMOS; SILICIDE/POLYSILICON LAYERS;

SEMICONDUCTOR DEVICES, MOS;

EID: 0026385714     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.116959     Document Type: Article

References (11)

1. G. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Devices, vol. ED-32, no. 3, p. 584, 1985.
2. C. L. Chu, K. C. Saraswat, and S. S. Wong, “Characterization of lateral dopant diffusion in silicides,” in IEDM Tech. Dig., 1990, p. 245.
3. C. Chu, “Measurement and modeling lateral dopant diffusion in silicides,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Tech. Rep. ICL91-007, June 1991.
4. H. Hayashida et al., “Dopant redistribution in dual gate W-polycide CMOS and its improvements by RTA,” in Symp. VLSI Technology Dig., 1989, p. 29.
5. M. E. Law, C. S. Rafferty, and R. W. Dutton, “SUPREM-IV users manual,” Stanford Univ., Stanford, CA, Tech. Rep., Dec. 1988.
6. M. R. Pinto, C. S. Rafferty, and R. W. Dutton, “PISCES II: Poisson and continuity equation solver,” Stanford Univ., Stanford, CA, Tech. Rep., Sept. 1984.
7. J. R. Pfiester et al., “A TiN strapped polysilicon gate cobalt silicide CMOS process,” in IEDM Tech. Dig., 1990, p. 241.
8. F. C. Shone, S. E. Hansen, D. B. Kao, K. C. Saraswat, and J. D. Plummer, “Modeling dopant redistribution in SiO2 /WSi2 /Si structure,” in IEDM Tech. Dig., 1986, p. 534.
9. F. C. Shone, “Physics and modeling of dopant redistribution in silicide/silicon shallow junction devices,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Dec. 1987.
10. F. C. Shone, K. C. Saraswat, and J. D. Plummer, “Formation of 0.1 &muml;m N +/P and P+/N junctions by doped silicide technology,” in IEDM Tech. Dig., 1985, p. 407.
11. D. L. Kwong et al., “Silicided shallow junction formation by ion implantation of impurity ions into the silicide layers and subsequent drive in,” J. Appi Phys., vol. 61, no. 11, p. 5084, 1987.