PRACTICAL TRENCH ISOLATION TECHNOLOGY WITH A NOVEL PLANARIZATION.

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1987, Pages 732-735

  Fuse, G ^a   Ogawa, H ^a   Tateiwa, K ^a   Nakao, I ^a   Odanaka, S ^a   Fukumoto, M ^a   Iwasaki, H ^a   Ohzone, T ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, DIGITAL - RANDOM ACCESS; DATA STORAGE, SEMICONDUCTOR; ETCHING; PHOTORESISTS;

ETCH-BACK BARRIER; NARROW-CHANNEL-EFFECT; SCC DYNAMIC RAM; TRENCH ISOLATION TECHNOLOGY; UNIFORM TOP-RESIST COATING;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0023593251     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)