Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

IEEE International Test Conference (TC)

Volumn , Issue , 1995, Pages 45-53

  Calin, Th ^a   Vargas, F L ^a   Nicolaidis, M ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; ERROR CORRECTION; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; MONITORING;

BUILT IN CURRENT SENSING; CURRENT MONITORING; MEMORY CELL UPSETS; SINGLE BIT DATA STORAGE ERRORS; SINGLE EVENT UPSETS; SOFT ERRORS;

RANDOM ACCESS STORAGE;

EID: 0029516848     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)