The Design of Radiation-Hardened ICS for Space: A Compendium of Approaches

Proceedings of the IEEE

Volumn 76, Issue 11, 1988, Pages 1470-1509

  Kerns, Sherra E ^a   Shafer, B D ^b  

^a VANDERBILT UNIVERSITY   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONICS--MATERIALS; RADIATION EFFECTS--COMPUTER SIMULATION;

HARDENED BIPOLAR DIGITAL LOGIC; HARDENED BULK/EPI CMOS CIRCUITS; HARDENED CMOS/SOS CIRCUITS; HETEROJUNCTION MESFET; RADIATION HARDENED INTEGRATED CIRCUITS;

INTEGRATED CIRCUITS;

EID: 0024104188     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/5.90115     Document Type: Article

References (73)

1. R. L. Pease, R. M. Turfler, D. Platteter, D. Emily, and R. Blice, “Total dose effects in recessed oxide digital bipolar microcircuits”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4216–4223, Dec. 1983.
2. T. E. Zipperianand T. J. Drummond, “Strained-quantum-well modulation-doped field effect transistor”, Electron. Lett., vol. 21, pp. 823–824, Aug. 1985.
3. J. R. Schwank et al., “Physical mechanisms contributing to device 'rebound'”, IEEE Trans. Nuclear Sci., vol. NS-31, no. 6, pp. 1434–1438, Dec. 1984.
4. E. L. Petersen, J. B. Langworthy, and S. E. Diehl, “Suggested single event upset figure of merit”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4533–4539, Dec. 1983.
5. James H. Adams, Jr., “The natural radiation environment inside spacecraft”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2095–2100, Dec. 1982.
6. H. E. Boesch, Jr., F. B. McLean, J. B. Benedetto, J. M. McCarrity, and W. E. Bailey, “Saturation of threshold voltage shift in MOSFET's at high total dose”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1191–1197, Dec. 1986.
7. J. M. Benedetto, H. E. Boesch, Jr., F. B. McLean, and J. P. Mize, “Hole removal in thin-gate MOSFETs by tunneling”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 3916–3920, Dec. 1985.
8. N. S. Saks, M. G. Ancona, and J. A. Modolo, “Generation of interface states by ionizing radiation in very thin MOS oxides”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1185–1190, Dec. 1986.
9. J. R. Schwank et al., “Radiation-induced interface-state generation in MOS devices”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1178–1184, Dec. 1986.
10. J. R. Hauser et al., “Ion track shunt effects in multi-junction structures”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4115–4121, Dec. 1985.
11. A. R. Knudson et al., “Charge transport by ion shunt effect”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1560–1564, Dec. 1986.
12. J. A. Zoutendyk, L. S. Smith, and G. A. Soli, “Experimental evidence for a new single-event upset ‘SEU’ mode in a CMOS SRAM obtained from model verification”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1292–1299, Dec. 1987.
13. K. Soliman and D. K. Nichols, “Latchup in CMOS devices from heavy ions”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4514–4519, Dec. 1983.
14. J. H. Stephen et al., “Cosmic ray simulation experiments for the study of single event upsets and latchup in CMOS memories”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4464–4469, Dec. 1983.
15. M. Shoga and D. Binder, “Theory of single event latchup in complementary metal-oxide semiconductor integrated circuits”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1714–1717, Dec. 1986.
16. Y. Taur et al., “A self-aligned 1-μm channel CMOS technology with retrograde n-well and thin epitaxy”, IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 123–129, Feb. 1985.
17. R. R. Troutman, “Epitaxial layer enhancement of n-well guard rings for CMOS circuits”, IEEE Electron Device Lett, vol. EDL-4, no. 12, pp. 438–440, Dec. 1983.
18. L. S. Smith, “Temperature and epi thickness dependence of the heavy ion induced latchup threshold for a CMOS/EPI16K static RAM”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1800–1803, Dec. 1987.
19. Y. Song et al., “Parametric investigation of latchup sensitivity in 1.25 μM CMOS technology”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1431–1437, Dec. 1987.
20. Y. Song, J. S. Cable, K. N. Vu, and A. A. Witteles, “The dependence of latchup sensitivity on layout features in CMOS integrated circuits”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1493–1498, Dec. 1986.
21. R. R. Troutman, Latchup in CMOS Technology: The Problem and Its Cure. Norwell, MA: Kluwer Academic Publishers, 1986.
22. A. B. Campbell et al., “Charge collection in CMOS/SOS structures”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4128–4132, Dec. 1985.
23. D. B. Estreich, A. Ochoa, Jr., and R. W. Dutton, “An analysis of latchup prevention in CMOS IC's using an epitaxial-buried layer process”, International Electron Devices Technical Dig., pp. 230-234, Dec. 1978.
24. P. J. McNutly, J. E. Lynch, and W. G. Abdel-Kader, “Effectiveness of CMOS charge reflection barriers in space radiation environments”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1796–1799, Dec. 1987.
25. D. S. Yaney and C. W. Pierce, “The use of thin epitaxial layers for MOS VLSI”, in International Electron Devices Meeting Technical Dig., pp. 237-238, Dec. 1981.
26. M. R. Wordeman, R. H. Dennard, and G. A. Sai-Halasz, “A buried N-grid for protection against radiation induced charge collection in electronic circuits”, in International Electron Devices Meeting Technical Dig., pp. 40-43, Dec. 1981.
27. R. S. Payne, L. C. Parrillo, R. E. Davis, G. W. Reutlinger, and R. L. Field, “Twin-tub CMOS-A technology for VLSI circuits”, in International Electron Devices Meeting Technical Dig., pp. 752-755, Dec. 1980.
28. J. R. Adams, W. R. Dawes, Jr., and T. S. Sanders, “A radiation-hardened field oxide”, IEEE Trans. Nuclear Sci., vol. NS-24, no. 6, pp. 2099–2101, Dec. 1977.
29. D. M. Fleetwood, P. V. Dressendorfer, and D. C. Turpin, “A reevaluation of worst-case postirradiation response for hardened MOS transistors”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1178–1183, Dec. 1987.
30. P. S. Winokur et al., “Total dose radiation and annealing studies: Implications for hardness assurance testing”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1343–1351, Dec. 1986.
31. A. H. Johnston, “Super recovery of total dose damage in MOS devices”, IEEE Trans. Nuclear Sci., vol. NS-31, no. 6, pp. 1427-1433, Dec. 1984.
32. H. Hatano and M. Shibuya, “CMOS logic circuit optimum design for radiation tolerance”, Electron. Lett, vol. 19, no. 23, pp. 977–979, Nov. 10, 1983.
33. C. M. Hsieh, P. C. Murley, and R. R. O'Brien, “A field-fun-neling effect on the collection of alpha-particle-generated carriers in silicon devices”, IEEE Electron Device Lett., vol. EDL-2, no. 4, pp. 103–105, Apr. 1981.
34. F. B. McLean and T. R. Oldham, “Charge tunneling in N-and P-type Si substrates”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2018–2023, Dec. 1982.
35. C. Hu, “Alpha-particle-induced field and enhanced collection of carriers”, IEEE Electron Device Lett., vol. EDL-3, no. 2, pp. 31–34, Feb. 1982.
36. G. C. Messenger, “Collection of charge on junction nodes from ion tracks”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2024–2031, Dec. 1982.
37. T. R. Oldham and F. B. McLean, “Charge collection measurements for heavy ions incident on N-and P-type silicon”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4493–4500, Dec. 1983.
38. T. R. Oldham, F. B. McLean, and J. M. Hartman, “Revised funnel calculations for heavy particles with high dE/dX”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1646–1650, Dec. 1986.
39. J. S. Fu, et al. “Processing enhanced SEU tolerance in high density SRAMs”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1322–1325, Dec. 1987.
40. S. E. Diehl, A. Ochoa, Jr., P. V. Dressendorfer, R. Koga, and W. A. Kolasinski, “Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMs”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2032–2039, Dec. 1982.
41. J. L. Andrews et al., “Single event error immune CMOS RAM”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2040–2043, Dec. 1982.
42. T. M. Mnich et al., “Comparison of analytical models and experimental results for single event upset in CMOS SRAMs”, IEEE Trans. Nuclear Sci., vol. NS-30, no. 6, pp. 4620–4623, Dec. 1983.
43. J. S. Browning, R. Koga, and W. A. Kolasinski, “Single event upset rate estimates for a 16-K CMOS SRAM”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4133–4139, Dec. 1985.
44. L. R. Rockett, Jr., “An SEU hardened CMOS data latch design”, to appear in IEEE Trans. Nuclear Sci., vol. NS-35, no. 6, Dec. 1988.
45. S. Muroga, VLSI System Design. New York, oNY: Wiley, 1982, pp. 213-217.
46. T. P. Haraszti, “CMOS/SOS memory circuits for radiation environments”, IEEE J. Solid-State Circuits, vol. SC-13, no. 5, pp. 669–676, Oct. 1978.
47. J. S. Brugler and P. G. A. Jestpers, “Charge pumping in MOS devices”, IEEE Trans. Electron Devices, vol. ED-16, no. 3, pp. 297–302, Mar. 1969.
48. A. Dingwall and R. Stewart, “16K CMOS/SOS asynchronous RAM”, IEEE’. Solid-State Circuits, vol. SC-14, no. 5, pp. 867-872, 1979.
49. J. G. Rollins and J. Choma, Jr., “Single event upset in SOS integrated circuits”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1713–1717, Dec. 1987.
50. W. A. Kolasinski et al., “Single event upset vulnerability of selected 4k and 16k CMOS static RAMs”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2044–2048, Dec. 1982.
51. G. Brucker, R. Smeltzer, W. A. Kolasinski, and R. Koga, “Soft error dependence of feature size and correlation with X-ray upset data”, IEEE Trans. Nuclear Sci., vol. NS-31, no. 6, pp 1562–1564, Dec. 1984.
52. S. Verghese, J. J. Wortman, and S. E. Kerns, “A novel CMOS SRAM feedback element for SEU environments”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1641–1646, Dec. 1987.
53. F.-L. Hsueh and L. S. Napoli, “CMOS/SOS high soft-error threshold memory cells”, IEEE Trans. NuclearSci., vol. NS-32, r.o. 6, pp. 4155–4158, Dec. 1985.
54. T. R. Weatherford, J. R. Hauser, and S. E. Diehl, “Comparison of single event vulnerability of GaAs SRAMs”, IEEE Trans. NuclearSci., vol. NS-33, no. 6, pp. 1590–1596, Dec. 1986.
55. R. L. Johnson and S. E. Diehl, “An improved single event resistive hardening technique for CMOS static RAMs”, IEEE Trans. NuclearSci., vol. NS-33, no. 6, pp. 4122–4127, Dec. 1986.
56. H. T. Weaver et al., “An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, Dec. 1987.
57. W. E. Price, J. C. Pickel, T. Ellis, and F. B. Frazee, “Cosmic ray induced errors in I2L Microprocessors and logic devices”, IEEE Trans. Nuclear Sci., vol. NS-29, no. 6, pp. 2064–2066, Dec. 1981.
58. A. L. Friedman et al., “Single event upset in combinatorial and sequential current mode logic”, IEEE Trans. NuclearSci., vol. NS-32, no. 6, pp. 4216–4217, Dec. 1985.
59. S. E. Diehl, J. E.Vinson, and E. L. Petersen, “Single event upset rate predictions for complex logic systems”, IEEE Trans. NuclearSci., vol. NS-31, no. 6, pp. 1132–1138, Dec. 1984.
60. L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits”, University of California, Berkeley, Memo ERL-M520, May 1975.
61. R. S. Wagner, J. M. Bradley, C. J. Maggiore, J. G. Beery, and R. H. Hammond, “An approach to measure ultrafast-fun-neling-current transients”, IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, pp. 1651–1655, Dec. 1986.
62. R. S. Wagner et al., “Transient measurements of ultrafast charge collection in semiconductor diodes”, IEEE Trans. Nuclear Sci., vol. NS-34, no. 6, pp. 1240–1245, Dec. 1986.
63. J. A. Zoutendyk, L. S. Smith, G. A. Soli, P. Thieberger, and H. E. Wegner, “Single-event upset ‘SEU’ model verification and threshold determination using heavy ions in a bipolar static RAM”, IEEE Trans. Nuclear Sci., vol. NS-31, no. 6, pp. 1167–1174, Dec. 1984.
64. J. R. Hauser et al., “Ion track shunt effects in multi-junction structures”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4114–4121, Dec. 1985.
65. A. Peczalski, J. Bergman, and D. Berndt, “Physical SEU model for circuit simulations”, to appear in IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, Dec. 1988.
66. J. S. Fu, H. T. Weaver, R. Koga, and W. A. Kolasinski, “Comparison of 2D memory SEU transport simulation with experiments”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4145–4149, Dec. 1985.
67. E. Jeffrey and G. Wilder, “Characterization of a radiation-hard 44 volt bipolar linear process”, to appear in IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, Dec. 1988.
68. A. W. Swanson, “Pseudomorphic HEMT”, Microwaves and RE, pp. 139-150, Mar. 1987.
69. N. G. Einspruch and W. R. Wisseman, VLSI Electronics microstructure Science, vol. 2: GaAs Microelectronics. New York, NY: Academic Press, 1985.
70. T. R. Weatherford, J. R. Hauser, and S. E. Diehl, “A study of single events in GaAs SRAMs”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4170–4175, Dec. 1985.
71. L. D. Flesner, “Gate charge collection and induced drain current in GaAs FETs”, IEEE Trans. Nuclear Sci., vol. NS-32, no. 6, pp. 4110–4114, Dec. 1985.
72. L. D. Flesner, R. Zuleeg and W. A. Kolasinski, “Comparison of heavy ion and electron-beam upset data for GaAs SRAMs”, to appear in IEEE Trans. Nuclear Sci., vol. NS-33, no. 6, Dec. 1988.
73. J.M. Golio, J. R. Hauser, and P. A. Blakley”, A large-signal GaAs MESFET model implemented on SPICE”, IEEE Circuits Devices Mag., vol. 1, no. 5, pp. 21–25, Sept. 1985.