An SEU-hardened CMOS data latch design

IEEE Transactions on Nuclear Science

Volumn 35, Issue 6, 1988, Pages 1682-1687

  Rockett, Leonard R ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATORS, CYCLOTRON; SEMICONDUCTOR DEVICES, MOS;

CMOS DATA LATCH; CMOS INTEGRATED CIRCUITS; RADIATION HARDNESS; SINGLE EVENT UPSETS;

INTEGRATED CIRCUITS;

EID: 0024169259     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.25522     Document Type: Article

References (3)

1. “Advanced Statistical Program (ASTAP),” Program Reference Manual, Program Number 5796-PBH, 1973.
2. W. B. Henley and N. F. Haddad, “Manufacturable Radiation Hardened 1.0 μM CMOS Technology for DoD Applications,” 1987 GOMAC Digest of Papers, Vol.13, No.1, pp. 115–118, October 1987.
3. S.E. Diehl, A. Ochoa Jr., P.V. Dressendorfer, R. Koga, W.A. Kolasinski, “Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs,” IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, pp. 2032–2039, December 1982.