Implementation of the FFT butterfly with redundant arithmetic

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 10, 1996, Pages 717-723

  Bruguera, J D ^a   Lang, T ^b  

^a UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FAST FOURIER TRANSFORMS; MATHEMATICAL MODELS;

CARRY SAVE ADDERS; REDUNDANT ARITHMETIC;

ADDERS;

EID: 0030258902     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.539004     Document Type: Article

References (15)

1. A. P. Chandrakasan. S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-Stale Circuits, vol. 27, pp. 473-484, Apr. 1992.
2. T. H. Chen and L. G. Chen, "Concurrent error-detectable butterfly chip for real-time processing through time redundancy," IEEE J. Solid-State Circuits, vol. 28, pp. 537-547, May 1993.
3. M. Ercegovac and T. Lang. Division and Square Root: Digit-Recurrence, Algorithms, and Implementations. Norwell, MA: Kluwer Academic, 1994.
4. A. Ghosli, S. Devaclas, K. Keutzer, and J. White, "Estimation of average switching activity in combinatorial and sequential circuits," Proc. 29th ACM/IEEE Design Autom. Conf, 1992, pp. 253-259.
5. S. Gomcz, S. Gonzalez, D. D. Hsu. and A. E. Kuo, "An application-specific FFT processor," Electron. Eng. Supplement, pp. 99-106, June 1988.
6. B. Holland and J. Mather, "Monolithic frequency domain processing with 450 MFLOPS throughput," Electron. Eng., pp. 29-36, Aug. 1989.
7. K. Hwang, Computer Arithmetic: Principles, Architecture and Design. New York: Wiley, 1979.
8. H. Miyanaga, H. Yamauchi, and K. Matsuda, "A real-time 256 X 256 point two-dimensional FFT single chip processor," Proc. IEEE Int. Conf. Acoust., Speech, Signal Processing, 1991, pp. 1193-1196.
9. M. Nagato, S. Tanaka, J. Mori, K. Hirano, T. Noguchi, and K. Hatanaka, "A 15-ns 32 x 32-b CMOS multiplier with and improved parallel structure," IEEE J. Solid-Slate Circuits, vol. 25, pp. 494-4197, Feb. 1990.
10. V. G. Oklobdzija and D. Villager, "Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology," Proc. Int. Symp. VLSI Techno!., Syst. Applical., 1993, pp. 209-212.
11. V. G. Oklobdzija. D. Villeger. and T. Soulas, "An integrated multiplier for complex number," J. VLSI Signal Processing, vol. 7, no. 3, pp. 213-222. 1994.
12. S. G. Peiilli, M. J. Grimm, and E. M. Oison, "A pipelined 45 MHz 24-bit digital signal processing ASIC," Proc. Asilomar Conf. Signals, Syst.. Comput., 1992. pp. 666-670.
13. L. R. Rabiner and B. Gold, Theory nnd Application of Digital Signal Processing, hnglewood Cliffs, NJ: Prentice-Hall, 1975.
14. P. A. Ruetz and M. M. Cai, ''A real time FFT chip set: Architectural issues," Proc. IEEE Int. Conf. Pattern Recog., 1990, pp. 385-388.
15. K. Yamashita, A. Kanasugi, S. Hijiya, G. Goto, N. MaKumura, and T. Shirato, "A wafer-scale 170 000-gate FFT processor with built-in test circuits," 1EEEJ. Solid-State Circuits, vol. 23, pp. 336-342, 1988.