-
1
-
-
84936429574
-
-
N.M. Marinovich, and V.G. Oklobdzija, “VLSI Chip Architecture for Real Time Ambiguity Function Computation,” 25th Asilomar Conference on Signals, Systems and Computers, November 4–6, Pacific Grove, 1991.
-
-
-
-
4
-
-
84936447685
-
-
Akinwande et al., “A 500 MHz 16×16 Complex Multiplier Using Self-Aligned Gate GaAs Heterostructure FET Technology,”IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, 1989.
-
-
-
-
5
-
-
84936392331
-
A Complex Integer Multiplier Using the Quadratic-Polynomial Residue Number System with Numbers of Form 22 n+1
-
(1987)
IEEE Transactions on Computer
, vol.100-136
, Issue.10
, pp. 1255-1258
-
-
Shyu, H.C.1
-
7
-
-
84936394062
-
-
J.S. Walther, “A Unified Algorithm for Elementary Functions,”SJCC, 1971, p. 379.
-
-
-
-
8
-
-
84936443496
-
-
H. Yoshimura et al., “A 50 MHz CMOS Geometrical Mapping Processor,”IEEE Transaction on Circuits and Systems, 1989, p. 1360.
-
-
-
-
9
-
-
84936377048
-
-
A.D. Booth, “A Signed Binary Multiplication Technique,”Q.J. Mech. Appl. Math., 1951, pp. 236–240.
-
-
-
-
10
-
-
84936407444
-
-
C.S. Wallace, “A Suggestion for a Fast Multiplier,”IEEE Transaction on Electronic Computers, Vol. EC-13, No. 1, 1964.
-
-
-
-
11
-
-
84936424159
-
-
Luigi Dadda, “Some Schemes for Parallel Multipliers,”Alta Frequenza, Vol. 34, No. 5, 1965.
-
-
-
-
12
-
-
84936386938
-
-
W.J. Stenzel, and W.J. Kubitz, “A Compact High-Speed Parallel Multiplication Scheme,”IEEE Transaction on Computers, Vol. C-26, No. 10, 1977.
-
-
-
-
13
-
-
84936410044
-
-
A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bulletin, Vol. 20, 1981.
-
-
-
-
14
-
-
84936421912
-
-
Mark R. Santoro, “Design and Clocking of VLSI Multipliers,” Technical Report No. CSL-TR-89-397, Stanford University, 1989.
-
-
-
-
15
-
-
84936411155
-
-
Mark R. Santoro, and Mark A. Horowitz, “SPIM: A Pipelined 64×64-Bit Iterative Multiplier,”IEEE Journal of Solid State Circuits, Vol. 24, No. 2, 1989.
-
-
-
-
16
-
-
84936441373
-
-
J. Mori et al., “A 10 nS 54×54-b Parallel Structured Full Array Multiplier with 0.5-u CMOS Technology,”IEEE Journal of Solid State Circuits, Vol. 26, No. 4, 1991.
-
-
-
-
17
-
-
84936402063
-
-
K.F. Pang et al., “Generation of High Speed CMOS Multiplier-Accumulators,” Proceedings of Int'l. Conference on Computer Design, Rye, New York, 1988.
-
-
-
-
19
-
-
84936402965
-
-
V.G. Oklobdzija, and E.R. Barnes, “Some Optimal Schemes for ALU Implementation in VLSI Technology,”7th Symposium on Computer Arithmetic ARITH-7, 1985, Urbana, Illinois.
-
-
-
-
20
-
-
84936393879
-
-
V.G. Oklobdzija, and E.R. Barnes, “On Implementing Addition in VLSI Technology,”Journal of Parallel Processing and Distributed Computing, No. 5, 1988, p. 716.
-
-
-
-
21
-
-
84936445595
-
-
B.D. Lee, and V.G. Oklobdzija, “Delay Optimization of Carry-Lookahead Adder Structure,”Journal of VLSI Signal Processing, Vol. 3, No. 4, 1991.
-
-
-
-
22
-
-
84936424652
-
-
V.G. Oklobdzija, and David Villeger, “Multiplier Design Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology,” 1993 International Symposium on VLSI Technology, Systems and Applications, 1993, Taipei, Taiwan.
-
-
-
|