Concurrent Error-Detectable Butterfly Chip for Real-Time FFT Processing Through Time Redundancy

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 5, 1993, Pages 537-547

  Chen, Thou Ho ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS; PROGRAM COMPILERS; SEMICONDUCTING SILICON;

CONCURRENT ERROR-DETECTABLE BUTTERFLY CHIP; REAL-TIME FFT PROCESSING; RECOMPUTATION STEP; TIME REDUNDANCY;

VLSI CIRCUITS;

EID: 0027592819     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.229402     Document Type: Article

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