Multiplier design utilizing improved column compression tree and optimized final adder in CMOS technology

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 1993, Pages 209-212

  Oklobdzija, Vojin G ^a   Villeger, David ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ESYCOM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FORESTRY; INTEGRATED CIRCUIT DESIGN; VLSI CIRCUITS;

ARRIVAL TIME; CMOS MULTIPLIERS; CMOS TECHNOLOGY; MULTIPLIER DESIGN; MULTIPLIER TREES; REDUCTION TECHNIQUES; SIGNAL ARRIVAL; SIGNAL PATHS;

ADDERS;

EID: 85039710762     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.1993.263604     Document Type: Conference Paper

References (7)

1. A. Weinberger, "4-2 Carry-Save Adder Module", IBM Technical Disclosure Bulletin., Vol. 23, January 1981.
2. Mark R. Santoro, "A Pipelined 64X64b Iterative Array Multiplier", Digest of Technical Papers Int'l Solid-State Circuits Conference, February 1988.
3. J. Mori et al, "A WnS 54X54-b Parallel Structured Full Array Multiplier with 0.5-u CMOS Technology", IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991.
4. Masato Nagamatsu et al, "A 15nS 32X32-bit CMOS Multiplier with an Improved Parallel Structure", in 1989 Digest of Technical papers, IEEE Custom Integrated Circuits Conference.
5. T. Soulas, D. Villeger, V. G. Oklobdzija, "An ASIC Multiplier for Complex Numbers", Proceedings of EURO-ASIC-93, The European Event in ASIC Design, Paris, France, February 22-25, 1993.
6. A. K. W. Yeung, R. K. Yu, "A Self-Timed Multiplier with Optimized Fnal Adder", Final Report for CS 2921 (Prof. Oklobdzija), University of California Berkeley, Fall 1989.
7. P. Song, G. De Michelli, "Circuit and Architecture Trade-offs for High Speed Multiplication, IEEE Journal of Solid State Circuits, Vol. 26, No. 9, September 1991.