A 15-ns 32 X 32-b CMOS Multiplier with an Improved Parallel Structure

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 2, 1990, Pages 494-497

  Nagamatsu, Masato ^a   Hatanaka, Kazuhisa ^a   Mori, Junji ^a   Hirano, Katsusi ^a   Noguchi, Tatsuo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICES, MOS;

27,704 TRANSISTORS; 4-2 COMPRESSOR; CMOS MULTIPLIER; MULTIPLIER LAYOUT AREA; PARALLEL MULTIPLIER; TRIPLE-LEVEL-METAL TECHNOLOGY;

COMPUTERS, DIGITAL;

EID: 0025413901     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.52175     Document Type: Article

References (8)

1. A. D. Booth, “A signed binary multiplication technique,” Quart. J. Mech Appl. Math., vol. 4, pp. 236–240, 1951.
2. C. S. Wallace, “A suggestion for fast multipliers,” IEEE Trans. Electron. Comput., vol. EC-13, pp. 14–17, Feb. 1964.
3. J. Iwamura et al., “A CMOS/SOS multiplier,” in ISSCC Dig. Tech. Papers, 1984, pp. 194–195.
4. Y. Kaji et al., “A 45ns 16×16 CMOS multiplier,” in ISSCC Dig. Tech. Papers, 1984, pp. 84–85.
5. Y. Owaki et al, “A 7.4ns CMOS 16×16 multiplier,” in ISSCC Dig. Tech. Papers, 1987, pp. 52–53.
6. R. Sharma et al., “A 6.75ns single level metal CMOS 16×16 multiplier,” in VLSI Circuits Dig. Tech. Papers, 1988, pp. 91–92.
7. A. E. Gamal et al., “A CMOS 32b Wallace tree multiplier-accumulator,” in ISSCC Dig. Tech. Papers, 1986, pp. 194–195.
8. M. R. Santoro and M. A. Horowitz, “SPIM: A pipelined 64 × 64-bit iterative multiplier,” IEEE J. Solid-State Circuits, vol. 24, pp. 487–493, Apr. 1989.