Hot-Carrier Degradation of Submicrometer p-MOSFET’s with Thermal/LPCVD Composite Oxide

IEEE Transactions on Electron Devices

Volumn 40, Issue 1, 1993, Pages 163-168

  Lee, Yung Huei ^a   Yau, Leo D ^a   Hansen, Ethan ^a   Chau, Robert ^a   Sabi, Babak ^a   Hossaini, Shahab ^a   Asakawa, Butch ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FABRICATION; HOT CARRIERS; OXIDES;

ELECTRON TRAPPING LEVELS; GATE OXIDES; HOT CARIER DEGRADATION; N-CHANNEL MOSFETS; SUBMICROMETER P-CHANNEL MOSFETS; THERMAL/LPCVD COMPOSITE OXIDE;

MOSFET DEVICES;

EID: 0027264187     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.249440     Document Type: Article

References (18)

1. G. Kawamoto, G. Magyer, and L. Yau, “Hot-carrier trapping in thin LPCVD SiO2 dielectrics” IEEE Trans. Electron Devices, vol. ED-34, pp. 2450-2455, 1987.
2. P. K. Roy, R. H. Doklan, E. P. Martin, S. F. Shive, and A. K. Sinha, “Synthesis and characterization of high quality ultra thin gate oxides for VLSI/ULSI circuits,” in IEDM Tech. Dig., 1988, pp. 714–717.
3. H. H. Tseng, P. Tobin, J. Hayden, and K. M. Chang, “Advantages of CVD stacked gate oxide for robust 0.5 μ m transistors,” in IEDM Tech. Dig., 1991, pp. 75–78.
4. M. Koyanagi, A. G. Lewis, R. A. Martin, T. Y. Huang, and J. Y.Chen, “Hot-carrier-induced punchthrough (HEIP) effect in sub-micrometer PMOSFET’s,” IEEE Trans. Electron Devices, vol. ED-34, pp. 839–844, 1987.
5. Y. Hiruta, K. Maeguchi, and K. Kanzaki, “Impact of hot electron trapping on half micron PMOSFETs with P + poly Si gate,” in IEDM Tech. Dig., 1986, pp. 718–721.
6. M.-S. Liang, C. Chang, W. Yang, C. Hu, and R. W. Brodersen, “Hot carrier induced degradation in thin gate oxide MOSFETs,” in IEDM Tech. Dig., 1983, pp. 186–189.
7. C. Hu, S. Tam, F.-C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-carrier-induced MOSFET degradation—Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, pp. 375–385, 1985.
8. Y. Tang, D. Kim, Y.-H. Lee, and B. Sabi, “Unified characterization of two-region gate bias stress in submicrometer p-channel MOS- FET’s,” IEEE Electron Device Lett., vol. 11, pp. 203–205, 1990.
9. T.-C. Ong, P. K. Ko, and C. Hu, “Hot-carrier current modeling and device degradation in surface-channel p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, pp. 1658–1666, 1990.
10. C. Y. Wei, Y. Nissan-Cohen, and H. H. Woodbury, “Evaluation of 850°C wet oxide as the gate dielectric in a 0.8 μm CMOS process,” IEEE Trans. Electron Devices, vol. 38, pp. 2433–2441, 1991.
11. M. E. Zvanut, J. F. Feigl, S. R. Butler, and S. L. Titcomb, “Electrical properties of silicon dioxide films fabricated at 700°C,” J. Electron. Mat., vol. 14, pp. 343–366, 1985.
12. J. Lee, I. C. Chen, and C. Hu, “Comparison between CVD and thermal oxide dielectric integrity,” IEEE Electron Device Lett., vol. EDL-7, pp. 506–509, 1986.
13. T. Hosaka, Y. Kato, Y. Kojima, Y. Hattori, S. Endo, M. Kamiya, and Y. Hayashi, “Ultra thin reliability CVD-SiO2film for VLSI’s,” in Extended Abstracts, Electrochemical Society 170th Meet., 1986, pp. 620–621.
14. I. C. Chen, S. Holland, and C. Hu, “Electrical breakdown in thin gate and tunneling oxides,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 333–342, 1985.
15. C. Hu, “Thin oxide quality,” in IEDM Tech. Dig., 1985, pp. 368–371.
16. E. Takeda and N. Suzuki, “An emperical model for device degradation due to hot-carrier injection,” IEEE Electron Device Lett., vol. EDL-4, pp. 111–113, 1983.
17. G. Dunn and J. Krick, “Channel hot-carrier stressing of reoxidized nitride oxide p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 901–906, 1991.
18. N. Lifshitz and G. Smolinsky, “Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric,” IEEE Electron Device Lett., vol. 12, no. 3, pp. 140–142, 1991.