IBAW: An implication-tree based alternative-wiring logic transformation algorithm

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 415-421

  Long, Wangning ^a   Wu, Yu Liang ^b   Bian, Jinian ^a  

^a TSINGHUA UNIVERSITY   (China)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OPTIMIZED; CIRCUIT PARTITIONING; DESIGN AUTOMATIONS; ITS APPLICATIONS; LOGIC OPTIMIZATION; LOGIC VALUES; SOURCE NODES; TRANSFORMATION ALGORITHM;

ALGORITHMS; COMPUTER AIDED DESIGN; ENGINES; FORESTRY; MULTIPROCESSING SYSTEMS; OPTIMIZATION; REDUNDANCY; TREES (MATHEMATICS); WIRE;

LOGIC CIRCUITS;

EID: 0010893730     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368720     Document Type: Conference Paper

References (14)

1. E M Sentovich, K J Singh, L Lavagno, et. al., "SIS: A System for Sequential Circuit Synthesis", ERL Memorandum No. UCB/ERL M92/41, 1992.
2. K-T Cheng and L A Entrena, "Multi-Level Logic Optimization By Redundancy Addition and Removal", in Proc. Europe Conf. Design Automation, 1993, pp. 373-377.
3. L A Entrena and K-T Cheng, "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal", IEEE Trans CAD of ICAS, Vol. 14, No. 7, July, 1995, pp. 909-916.
4. W Kunz and P R Menon, "Multilevel Logic Optimization by Implication analysis", in ICCAD94, 1994, pp. 6-13.
5. M Chatterjee, D K Pradhan, and W Kunz, "LOT: Logic Optimization with Testability - New Transformations for Logic Synthesis", IEEE Trans CAD of ICAS, Vol. 17, No 5, May 1998, pp. 386-399. (Pubitemid 128742034)
6. S-C Chang, M Marek-Sadowska, and K-T Cheng, "Perturb and Simplify: Multilevel Boolean Network Optimizer", IEEE Trans CAD of ICAS, Vol. 15, No. 12, Dec 1996, pp. 1494-1504. (Pubitemid 126780411)
7. S-C Chang, L P V Ginneken, and M Marek-Sadowska, "Fast Boolean Optimization by Rewiring", In Proc ICCAD'96, 1996, pp. 262-269.
8. H Ichihara, K Kinoshita. "Logic Optimization: Redundancy Addition and Removal Using Implication Relationships", IEICE Trans Inf. & Syst, E81-D(7), 1998, pp. 724-730. (Pubitemid 128728901)
9. th International Symposium on Fault Tolerant computing, 1983, pp. 98-105.
10. W Kunz and D K Pradham, "Recursive Learning: An Attractive Alternative to the decision Tree for Test Generation for Digital Circuit", in Proc. Int. Test Conf., 1992, pp. 816-825.
11. S-S Chang, K-T Cheng, N-S Woo, and M Marek-Sadowska, "Postlayout Logic Restructuring Using Alternative Wires", IEEE Trans CAD of ICAS, Vol. 16, No. 6, June 1997, pp. 587-596.
12. th DAC, 1997, pp. 662-665.
13. D I Cheng, C-C Lin, and M Marek-Sadowska, "Circuit Partitioning with Logic Perturbation", in Proc. ICCAD'95, 1995, pp. 650-655.
14. W Long, "Study on Alternative Wiring Logic Synthesis System", Post-doctoral Research Report, Tsinghua University, Beijing, China, 1999.