Off chip monitors and built in current sensors for analogue and mixed signal testing

Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

Volumn 1998-November, Issue , 1998, Pages 59-63

  Maidon, Y ^a   Deval, Y ^a   Manhaeve, H ^b  

^a UNIVERSITÉ BORDEAUX 1   (France)

^b Katholieke Hogeschool Brugge Oostende   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN CURRENT SENSORS; CURRENT MONITORS; DC POWER SUPPLIES; MIXED-SIGNAL TESTING; POWER SUPPLY CURRENT; SENSITIVE ELEMENTS; STATE OF THE ART; TRANSIENT POWER SUPPLY;

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 0002643850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1998.730758     Document Type: Conference Paper

References (35)

1. S.R. Makar and E.J. McCluskey, "Some Faults Really Needs an IDDQ Test", Digest of Papers, IEEE Inter. Workshop on IDDQ Testing, 1996, pp. 102-103.
2. H. Yamazaki and Y. Miura, "IDDQ Testability of Flip-flop Structures", Digest of Papers, IEEE Inter. Workshop on IDDQ Testing, 1996, pp. 29-33.
3. Y. Maidon, Y. Deval, H. Fremont and J.P. Dom, "Using IDD to Analyse Analogue Faults and Development of a Sensor", Proc. of Micro-electronic Manufacturing Yield, Reliability and Failure Analysis", October 1996, pp. 152-161, vol. 2874.
4. M.K. Reddy and S.M. Reddy, "Detecting FET Stuck-Open Faults in CMOS Latches and Flip-flops", IEEE Design and Test Computers, vol. 3, no 5, October 1986, pp. 17-26.
5. K.J. Lee and M.A. Bruer, "A Universal Test Sequence for CMOS Scan Registers", CICC, 1990, pp. 1-4.
6. W.K. Al-Assadi, "Faulty Behavior of Storage Elements and Its Effects on Sequential Circuits", IEEE Trans. on VLSI, 1993, vol. 1, no 4.
7. R. Rasjuman, »IDDQ Testing for CMOS VLSI », Artech House, 1995.
8. T.W. William, R. Kapur and M.R. Mercer, « IDDQ Testing for High Performance CMOS - The Next Ten Years », ED&TC'96, Paris, 1996.
9. M. Sachdev and H. Kerkhoff, "IDDQ Testable Dynamic PLAs", Digest of Papers, IEEE Inter. Workshop on IDDQ Testing, 1997, pp. 17-22.
10. M. Sachdev, "Reducing the CMOS RAM Test Complexity with IDDQ and Voltage Testing", JETTA, April 1995, no 2, pp. 191-202.
11. A. Materka and M. Strzelechi, "Parametric Testing of CMOS Circuits by ANN Based Processing of Transient Power Supply Current", IMSTW'95, June 1995, pp. 223-227.
12. K.M. Wallquist, A.V. Righter and C.F. Hawkins, « A General purpose IDDQ Measurement Circuit », ITC'93, October 1993, pp. 642-651.
13. H. Manhaeve, P.L. Wrighton, J. van Sas and U. Swerts, « An Off-Chip IDDQ Current Measurement Unit for Telecommunication ASICs », ITC'94, October 1994, paper 7.2.
14. K. Baker, A. Bratt, A. Richardson and A. Welbers, « Development of a class 1 QTAG Monitor », ITC'94, October 1994, pp. 213-222.
15. Pedros, A. Rubio and J. Segura, « An Integrated Standard Interface Sensor for IDDQ Testing », ITC'95, 1995, pp.50-53.
16. G.H. Jonhson and J.B. Wilsturp, « A General Purpose ATE based IDDQ Measurement Circuit », ITC'95, 1995, pp. 97-105.
17. B. Straka, H. Manhaeve and J. Vanneuville, « Programmable Off-Chip IDDQ Monitor », ED&TC'97, 1997, pp. 99-102.
18. K. Isawa and Y. Hashimoto, « High Speed IDDQ Measurement Circuit », ITC'96, 1996, pp. 112-115.
19. V. Stopjakova and H. Manhaeve, « CCII + Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits », ED&TC'97, 1997, pp. 226-269.
20. M. Keating and D. Meyer, « A New Approach to dynamic IDD Testing », ITC, September 1987, pp. 316-321.
21. Y. Maidon, Y. Deval, J. Tomas and J.B. Begueret, « On-Line CMOS BICS : An experimental study », Digest of paper, IDDQ'97, November 1997, pp. 85-89.
22. K.M. Wallquist, "Achieving IDDQ/ISSQ Production Testing with QuiC-Mon", IEEE Design & Test of Computers, 1995, vol. 12, no3, pp. 92-69.
23. M. Hashizume, M. Ichimiya and T. Tamesada, « A Current Sensing Circuit for Feedback Bridging Faults », Digest of paper, IDDQ'97, November 1997, pp. 110-113.
24. H. Manhaeve, M. Svajda and B. Straka, « Off-Chip IDDQ Monitor Developments : From OCIMU to DOCIMU and IOCIMU », Hot Topic Workshop CTAMS, February 1998.
25. Y. Maidon, Y. Deval, P. Fouillat, J. Tomas, J.P. Dom, «On chip IDDX sensor », IDDQ'96, October 1996, pp. 64-66.
26. T.C. Huang, M.C. Huang and K.J. Lee, « A High Speed Low Voltage Current Sensor », Digest of paper, IDDQ'97, November 1997, pp. 90-94.
27. T.L. Shen, J.C. Daly and J.C. Lo, « A 2ns Detecting Time, 2μm CMOS Built-In Current Sensing Circuit », IEEE Jnl Solid-State Circuits, January 1993, vol. 28, no1, pp. 72-77.
28. A. Walker and P.K. Lala, « An Approach for Detecting Brindging Faults in Static CMOS Circuits using Dynamic Power Supply Current monitoring », Digest of paper, IDDQ'97, November 1997, pp. 73-77.
29. S.M. Menon and M. Palmgren, « Estimation of Partition Size for IDDQ Testing using Built-In Current Sensing », Digest of paper, IDDQ'97, November 1997, pp. 68-72.
30. W. Maly and P. Nigh, « Built-In Current Testing -Feasibility Study", IEEE ICCAD, November, 1988, pp. 340-343.
31. J. Rius and J. Figueras, « Proportional BIS Sensor for Current Testing", Journal of Electronic Testing : Theory and Applications 3, Dec. 1992, no4, pp. 387-396.
32. C.W. Hsue and C.J. Lin, « Built-In Current Sensor for IDDQ Test in CMOS", ITC, 1993, pp. 635-641.
33. J.P. Hurst and A.D. Singh, « A Differential Built-In Current Sensor Design for High-Speed IDDQ Testing", IEEE Journal of Solid-State Circuits, Jan. 1997, vol. 32, no1, pp. 122-125.
34. J.P.M. van Lammeren, "ICCQ : A Test Method for Analogue VLSI Based on Current Monitoring", IDDQ Testing, Nov. 97, pp. 24-28.
35. Y. Maidon, Y. Deval, J-B. Begueret, J.P. Dom, « High Sensitivity CMOS BICS », ETW'98, May 27-28, 1998, pp. 197-198.