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Volumn , Issue , 1996, Pages 29-33

IDDQ testability of flip-flop structures

Author keywords

[No Author keywords available]

Indexed keywords

SPICE;

EID: 0347391922     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1996.557806     Document Type: Conference Paper
Times cited : (5)

References (16)
  • 1
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    • Levi, M.1
  • 3
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    • Test generation for current testing
    • February
    • P. High and W. Maly, "Test Generation for Current Testing," IEEE Design &Test of Computers, Vol.7, No.l, pp. 26-38, February 1990.
    • (1990) IEEE Design &Test of Computers , vol.7 , Issue.1 , pp. 26-38
    • High, P.1    Maly, W.2
  • 6
    • 0027794558 scopus 로고
    • CMOS bridges and resistive transistor faults: IDDq versus delay effects
    • H.T. Vierhaus, W. Meyer and U. Glaser, "CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects," Proc. Int. Test Conf., pp. 83-91, 1993.
    • (1993) Proc. Int. Test Conf. , pp. 83-91
    • Vierhaus, H.T.1    Meyer, W.2    Glaser, U.3
  • 8
    • 0002238418 scopus 로고
    • Circuit design for built-in current testing
    • Y. Miura and K. Kinoshita, "Circuit Design for Built-in Current Testing," Proc. Int. Test Conf., pp. 873-881, 1992.
    • (1992) Proc. Int. Test Conf. , pp. 873-881
    • Miura, Y.1    Kinoshita, K.2
  • 9
    • 0027148018 scopus 로고
    • A 2-ns Detecting Time, 2mm CMOS Built-in Current Sensing Circuit
    • T.L. Shen, J.C. Daly and J.C. Lo, "A 2-ns Detecting Time, 2mm CMOS Built-in Current Sensing Circuit," IEEE, J.Solid-State Circuits,Vol.28,No.l, pp. 72-77,1993.
    • (1993) IEEE, J.Solid-State Circuits , vol.28 , Issue.1 , pp. 72-77
    • Shen, T.L.1    Daly, J.C.2    Lo, J.C.3
  • 10
    • 85068231432 scopus 로고
    • A built-in iddq test circuit utilizing upper and lower limets
    • Y. Miura and S. Naito, "A Built-in IDDQ Test Circuit Utilizing Upper and Lower Limets," Proc. Asia Test Symp., pp. 138143, 1994.
    • (1994) Proc. Asia Test Symp. , pp. 138143
    • Miura, Y.1    Naito, S.2
  • 11
    • 0001457657 scopus 로고
    • A practical current sensing technique for IDDq testing
    • J.J. Tang, K.J. Lee and B.D. Liu, "A Practical Current Sensing Technique for IDDQ Testing," IEEE Trans. VLSI Systems, Vol.3, No.2, pp. 302-310, 1995.
    • (1995) IEEE Trans. VLSI Systems , vol.3 , Issue.2 , pp. 302-310
    • Tang, J.J.1    Lee, K.J.2    Liu, B.D.3
  • 14
    • 0027961752 scopus 로고
    • Analysis of bridging defects in sequential CMOS circuits and their current testability
    • R. Rodriguez-Montanes and J. Figueras, "Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability," Proc. European Design &Test Conf., pp. 356360, 1994.
    • (1994) Proc. European Design &Test Conf. , pp. 356360
    • Rodriguez-Montanes, R.1    Figueras, J.2
  • 15
    • 0029493132 scopus 로고
    • IDDQ and voltage testable CMOS flip-flop configuration
    • M. Sachdev, "IDDQ and Voltage Testable CMOS Flip-flop Configuration," Proc. Int. Test Conf., pp. 534-543,1995.
    • (1995) Proc. Int. Test Conf. , pp. 534-543
    • Sachdev, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.