Transmission Line Pulse Testing of the ESD Protection Structures of ICs.- A Failure Analysts Perspective

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn , Issue , 2000, Pages 203-213

  Henry, Leo G ^a   Barth, Jon ^b   Richner, John ^b   Verhaege, Koen ^c  

^a ESD/TLP Consulting   (United States)

^b Barth Electronics Inc   (United States)

^c SARNOFF CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANODES; CMOS INTEGRATED CIRCUITS; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC LINES; ELECTRIC POTENTIAL; ELECTRONIC EQUIPMENT TESTING; FAILURE ANALYSIS; LEAKAGE CURRENTS; SCANNING ELECTRON MICROSCOPY; THYRISTORS;

ELECTRICAL FAILURE SIGNATURES; HUMAN BODY MODELS (HBM); TRANSMISSION LINE PULSES (TLP);

INTEGRATED CIRCUITS;

EID: 0002583356     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (38)

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