Statistical metrology for characterizing CMP processes

Microelectronic Engineering

Volumn 33, Issue 1-4, 1997, Pages 231-240

  Prasad, Sharad ^a   Loh, W ^a   Kapoor, A ^a   Chang, E ^b   Stine, B ^b   Boning, D ^b   Chung, J ^b  

^a AGERE SYSTEMS   (United States)

^b Department of Electrical Engineering and Computer Science   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL POLISHING; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

CHEMICAL MECHANICAL POLISHING (CMP); STATISTICAL METROLOGY;

MICROELECTRONIC PROCESSING;

EID: 0030856322     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0167-9317(96)00052-4     Document Type: Article

References (3)

1. E. Chang et al., IEDM Tech. Digest (1995).
2. R. Divecha et al., Proc. 1st IEEE Int. Workshop on Statistical Metrology, June 1996.
3. B. Stine et al., VMIC (1996).