Layout-Synthesis Techniques for Yield Enhancement

IEEE Transactions on Semiconductor Manufacturing

Volumn 8, Issue 2, 1995, Pages 178-187

  Koren, Israel ^a   Chiluvuri, Venkat K R ^b  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

^b UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER AIDED MANUFACTURING; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANT COMPUTER SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; OPTIMIZATION; VLSI CIRCUITS;

LAYOUT SYNTHESIS THICKNESS; RANDOM POINT DEFECTS; TOPOLOGICAL OPTIMIZATION; WAFER SCALE INTEGRATED SYSTEMS; YIELD ENHANCEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029306598     PISSN: 08946507     EISSN: 15582345     Source Type: Journal    
DOI: 10.1109/66.382281     Document Type: Article

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