Multiple clocking scheme for low power RTL design

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1995, Pages 27-32

  Papachristou, Christos ^a   Spining, Mark ^a   Nourani, Mehrdad ^a  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; ELECTRIC LOSSES; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; POWER ELECTRONICS; VLSI CIRCUITS;

MULTIPLE CLOCKING SCHEME; REGISTER TRANSFER LEVEL (RTL); SPARCSTATION MACHINES;

ELECTRIC NETWORK SYNTHESIS;

EID: 0029178790     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)