Input ordering in concurrent checkers to reduce power consumption

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 87-95

  Mohanram, K ^a   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Circuit faults; Concurrent computing; Costs; Crosstalk; Electrical fault detection; Energy consumption; Error correction; Fault detection; Fault tolerant systems; Integrated circuit noise

Indexed keywords

COST FUNCTIONS; COSTS; CROSSTALK; DESIGN FOR TESTABILITY; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; ENERGY UTILIZATION; ERROR CORRECTION; ERROR DETECTION; FAULT DETECTION; FAULT TOLERANCE; OPTIMIZATION; VLSI CIRCUITS;

CIRCUIT FAULTS; CONCURRENT COMPUTING; ELECTRICAL FAULT DETECTIONS; FAULT TOLERANT SYSTEMS; INTEGRATED CIRCUIT NOISE;

ELECTRIC POWER UTILIZATION;

EID: 9244233205     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173505     Document Type: Conference Paper

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