Tree checkers for applications with low power-delay requirements

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 213-220

  Metra, Cecilia ^a   Favalli, Michele ^a   Ricco, Bruno ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; CMOS INTEGRATED CIRCUITS; ENERGY UTILIZATION; INSTRUMENT TESTING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RELIABILITY;

SELF CHECKING CIRCUITS;

VLSI CIRCUITS;

EID: 0030395801     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)