Transistor reordering for power minimization under delay constraint

ACM Transactions on Design Automation of Electronic Systems

Volumn 1, Issue 2, 1996, Pages 280-300

  Prasad, S G ^a,b   Roy, K ^a,b  

^a TEXAS INSTRUMENTS   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

Circuit optimization; Critical path enumeration; Gate input reordering; Power estimation; Transistor reordering

Indexed keywords

EID: 0005412695     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/233539.233543     Document Type: Article

References (26)

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