In-line defect reduction from a historical perspective and its implications for future integrated circuit manufacturing

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 4, 2004, Pages 629-640

  Guldi, Richard L ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Defect root cause analysis; Historical yield learning; In line defect inspection; Yield modeling

Indexed keywords

CONTAMINATION; DIES; FABRICATION; PROCESS CONTROL; SILICON WAFERS; STACKING FAULTS;

DEFECT ROOT CAUSE ANALYSIS; HISTORICAL YIELD LEARNING; IN-LINE DEFECT INSPECTION; YIELD MODELING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 9144274556     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.835717     Document Type: Article

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