Application of defect inspection in development of 0.25 and 0.18 micron technology

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 135-138

  Guldi, R ^a   Winter, T ^a   PapaRao, S ^a   Smith, J ^a   Sridhar, N ^a   Garvin, J ^a   Metteer, B ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; CRYSTAL DEFECTS; ELECTRIC FAULT CURRENTS; FORMAL LOGIC; INSPECTION; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SENSITIVITY ANALYSIS;

BACK END OF LINES; CONTINUOUS IMPROVEMENTS; CRITICAL AREA ANALYSIS; DEFECT MONITORING; ELECTRICAL FAULTS; MICRON TECHNOLOGIES; SYSTEMATIC DEFECTS; TECHNOLOGY DEVELOPMENT;

DEFECTS; SEMICONDUCTOR DEVICE MANUFACTURE;

CRITICAL AREA ANALYSIS;

EID: 0033355830     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808756     Document Type: Conference Paper

References (4)

1. C. H. Stapper, AN. McLaren, and M. Dreekmann, "Yield Model for Producti vity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product", IBM 1. Re. l'. J D'velop. , vol. 24, pp. 398, (1980).
2. 2] R. GIang, "Defect Size Distributions in VLSI Chips", JERE Trans. Semiconductor Manl!tllcturing, vol. 4, pp. 265, (1991).
3. R. L. GuIdi, J. Watts, S. PapaRao, D. Catlett, J. Montgomery, and T, Sacki, " Analysis and Modeling of Systematic and Defect Related Yield Issues During Early Development of a New Technology", IEEE Advanced Semiconductor Manufacturing COllference, pp. 7-12, September [998.
4. Charles Wcher, "Standard Defect Monitor", 1998 IEEE Proc. On Microelectronic Test Structures, vol. I, pp. 144, (1988).