Parasitic extraction: Current state of the art and future trends

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 5, Issue , 2001, Pages 487-490

  Kao, William H ^a   Lo, Ch Yuan ^b   Singh, Raminderpal ^b   Basel, Mark ^c  

^a MAGMA DESIGN AUTOMATION   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c Alchemy Semiconductor   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; DEEP SUB-MICRON DESIGNS; DELAY CALCULATION; INTERCONNECT MODELING; PARASITIC EFFECT; PARASITIC EXTRACTION; SIGNAL INTEGRITY; STATE OF THE ART;

EXTRACTION;

EID: 85087192545     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2001.922091     Document Type: Conference Paper

References (16)

1. M. Kamon, S. McCorrnick, and K. Shepard, "Interconnect Parasitic Extraction in the Digital IC Design Methodology, " Proc. ICCAD, pp. 223-230, Nov. 1999.
2. B. Gieseke, et al, "A 600Mhz Superscalar RISC Microprocessor with Out of Order Execution, " ISSCC 97, pp. 176-177, San Francisco, 1997.
3. D. Edelstein and et al, "Full copper wiring in a sub-0.25um CMOS ULSI tecnology, " Proc. IEDM, pp.773-776, 1997.
4. R. Singh, 'A Review of Substrate Coupling Issues and Modeling Strategies, " Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 491-499, 1999.
5. N.K. Verghese, D. Allstot, "SUBTRACT: a program for the efficient evaluation of substrate parasitics hi integrated circuits, " 1995 Proc. ICCAD, pp. 194-198, 1995.
6. K. Nabors and J. White, "FastCap: A Multipole-Accelerated 3-D Capacitance Extraction Program, " IEEE Trans, on CAD, Vol. 10, No. 11, pp. 1447-1459, Nov. 1991.
7. W. Shi, J. Liu, N. Kakani, and T. Yu, "A Fast Hierarchical Algorithm for 3-D Capacitance Extraction, " Proc. 29th ACM/IEEE DAC, pp. 212-217, San Francisco, CA, June 1998.
8. U. Choudhury and A. Sangiovanni-Vicentelli, "Automatic generation of analytical models for interconnect capacitances, " IEEE Trans, on Computer-Aided Design of Integrated Circuits and Systems, 14(4):470-480, April 1995.
9. Narain D. Arora, Kartik V. Roal, Reinhard Schumann., and Llanda M. Richardson, "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits", IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, 15(1): pp. 58-67, January 1996.
10. Y. Ismail, E. Friedman, J. Neves, "Figures of Merit to Characterize the Importance of On-Chip Inductance, " Proceedings of the International Conference on Design Automation, pp. 560-565, 1998.
11. W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers, " J. Applied Physics. Vol. 19, No. 11, pp. 55-63, Jan 1948.
12. J. E. Bracken, V. Raghavan, and R. Rohrer, "Interconnect Simulation with Asymptotic Waveform Evaluation, " IEEE Trans. Circuits and Systems, pp. 869-878, Nov. 1992.
13. B. Tutuianu, F. Dartu and L. Pileggi, " An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response, " Proc. 33ld ACM/IEEE DAC, pp. 611-616, June 1996.
14. Y. Ismail, E. Friedman, and J. Neves, "Equivalent Elmore Delay for RLC Trees, " IEEE Trans. On CAD, Vol. 19, No. 1, pp. 83-97, Jan 2000.
15. Y. Ismail, E. Friedman, and J. Neves, " Repeater insertion in Tree Structured Inductive Interconnect, " Proc. 36th DAC, pp. 420-424, June 1999.
16. P. Saxena and C.L. Liu, "Crosstalk Minimization using Wiring Perturbations, " Proc. 36th Design Automation Conference, pp. 100-103, New Orleans, LA, June 1999.