Multicore performance optimization using partner cores

3rd USENIX Workshop on Hot Topics in Parallelism, HotPar 2011

Volumn , Issue , 2011, Pages

  Lau, Eric ^a   Miller, Jason E ^a   Choi, Inseok ^b   Yeung, Donald ^b   Amarasinghe, Saman ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; GENERAL PURPOSE COMPUTERS;

APPLICATION PROGRAMMERS; CHIP MULTIPROCESSOR; EMBEDDED PROCESSORS; GENERAL PURPOSE PROCESSORS; OPTIMIZATION CODE; OPTIMIZING PERFORMANCE; PERFORMANCE COUNTERS; PERFORMANCE OPTIMIZATIONS;

PARALLEL PROCESSING SYSTEMS;

EID: 85081543304     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)

1. A. AGARWAL. Realizing a Power Efficient, Easy to Program Many Core: The Tile Processor. Presented at the Stanford Computer Systems EE380 Colloquium. Available online: http://www.stanford.edu/class/ee380/Abstracts/100203-slides.pdf.
2. ANNAVARAM, M., PATEL, J. M., AND DAVIDSON, E. S. Data Prefetching by Dependence Graph Precomputation. In Proceedings of the 28th Annual International Symposium on Computer Architecture (Goteborg, Sweden, June 2001), ACM.
3. BARON, M. Low-Key Intel 80-Core Intro: The Tip of the Iceberg. Microprocessor Report (April 2007).
4. BHAVNAGARWALA, A., KOSONOCKY, S., KOWALCZYK, S., JOSHI, R., CHAN, Y., SRINIVASAN, U., AND WADHWA, J. A transregional CMOS SRAM with single, logic V and dynamic power rails. In Symp. VLSI Circuits Dig. Tech. Papers (2004), pp. 292-293.
5. DALTON, M., KANNAN, H., AND KOZYRAKIS, C. Raksha: a flexible information flow architecture for software security. In ISCA '07: Proceedings of the 34th Annual International Symposium on Computer Architecture (2007).
6. DOWECK, J. Inside the CORE microarchitecture. In presented at the 18th IEEE Hot Chips Symp. (Palo Alto, CA, August 2006).
7. GROCHOWSKI, E., AND ANNAVARAM, M. Energy per instruction trends in. Intel microprocessors. Technology Intel Magazine 4, 3 (2006), 1-8.
8. HOFFMANN, H., EASTEP, J., SANTAMBROGIO, M. D., MILLER, J. E., AND AGARWAL, A. Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments. In ICAC (2010).
9. HOFFMANN, H., SIDIROGLOU, S., CARBIN, M., MISAILOVIC, S., AGARWAL, A., AND RINARD, M. C. Dynamic knobs for responsive power-aware computing. In ASPLOS (2011), pp. 199-212.
10. KIM, D., WEI LIAO, S. S., WANG, P., DEL CUVILLO, J., TIAN, X., ZOU, X., WANG, H., YEUNG, D., GIRKAR, M., AND SHEN, J. Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. In Proceedings of the 2004 International Symposium on Code Generation and Optimization with Special Emphasis on Feedback-Directed and Runtime Optimization (San Jose, CA, March 2004).
11. KIM, D., AND YEUNG, D. Design and Evaluation of Compiler Algorithms for Pre-Execution. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA, October 2002), ACM, pp. 159-170.
12. KIM, D., AND YEUNG, D. A Study of Source-Level Compiler Algorithms for Automatic Construction of Pre-Execution Code. ACM Transactions on Computer Systems 22, 3 (August 2004).
13. KUMAR, R., JOUPPI, N., AND TULLSEN, D. Conjoined-Core Chip Multiprocessing. In Proc. Int'l Symp. Microarchitecture (2004), IEEE CS Press, pp. 195-206.
14. KWONG, J., RAMADASS, Y., VERMA, N., AND CHANDRAKASAN, A. A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched Capacitor DC-DC Convertor. IEEE Journal of Solid-State Circuits 44, 1 (January 2009), 115-125.
15. LEE, J., JUNG, C., LIM, D., AND SOLIHIN, Y. Prefetching with Helper Threads for Loosely Coupled Multiprocessor Systems. IEEE Transactions on Parallel and Distributed Systems 20, 9 (July 2009).
16. LU, J., DAS, A., HSU, W.-C., NGUYEN, K., AND ABRAHAM, S. G. Dynamic Helper Threaded Prefetching on the Sun Ultra-SPARC CMP Processor. In Proceedings of the 38th International Symposium on Microarchitecture (November 2005).
17. LUEBKE, D., HARRIS, M., KRUGER, J., PURCELL, T., GOVINDARAJU, N., BUCK, I., WOOLLEY, C., AND LEFOHN, A. GPGPU: general purpose computation on graphics hardware. In ACM SIGGRAPH 2004 Course Notes SIGGRAPH '04 (Los Angeles, CA, 2004), ACM.
18. MILLER, J., KASTURE, H., KURIAN, G., III, C. G., BECKMANN, N., CELIO, C., EASTEP, J., AND AGARWAL, A. Graphite: A Distributed Parallel Simulator for Multicores. In 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA) (January 2010).
19. MUKHERJEE, S., KONTZ, M., AND REINHARDT, S. Detailed Design and Evaluation of Redundant Multithreading Alternatives. In ISCA '02: Proceedings of the 29th Annual International Symposium on Computer Architecture (2002).
20. ROGERS, A., CARLISLE, M., REPPY, J., AND HENDREN, L. Supporting Dynamic Data Structures on Distributed Memory Machines. ACM Transactions on Programming Languages and Systems 17, 2 (March 1995).
21. TAYLOR, M. B., LEE, W., MILLER, J. E., WENTZLAFF, D., BRATT, I., GREENWALD, B., HOFFMANN, H., JOHNSON, P., KIM, J., PSOTA, J., SARAF, A., SHNIDMAN, N., STRUMPEN, V., FRANK, M., AMARASINGHE, S., AND AGARWAL, A. Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In ISCA '04: Proc of the 31st annual International Symposium on Computer Architecture (June 2004), pp. 2-13.
22. WENTZLAFF, D., GRIFFIN, P., HOFFMANN, H., BAO, L., EDWARDS, B., RAMEY, C., MATTINA, M., MIAO, C.-C., BROWN, J. F., AND AGARWAL, A. On-chip interconnection architecture of the Tile processor. IEEE Micro 27, 5 (Sept-Oct 2007), 15-31.
23. ZHAI, B., NAZHANDALI, L., OLSON, J., REEVES, A., MINUTH, M., HELFAND, R., PANT, S., BLAAUW, D., AND AUSTIN, T. A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency. In Symp. VLSI Circuits Dig. Tech. Papers (June 2006), pp. 154-155.
24. ZILLES, C., AND SOHI, G. Execution-Based Prediction Using Speculative Slices. In Proceedings of the 28th Annual International Symposium on Computer Architecture (Goteborg, Sweden, June 2001).