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Volumn 7, Issue 9, 2018, Pages

Hardware acceleration for RLNC: A case study based on the xtensa processor with the tensilica instruction-set extension

Author keywords

Application specific instruction set processor (ASIP); Flexible length instruction extension (FLIX); Galois field; Hardware acceleration; Multiply accumulate (MAC) operations; Random linear network coding (RLNC); Single instruction multiple data (SIMD)

Indexed keywords


EID: 85053630811     PISSN: None     EISSN: 20799292     Source Type: Journal    
DOI: 10.3390/electronics7090180     Document Type: Article
Times cited : (13)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.