Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers

2016 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2016 - Proceedings

Volumn , Issue , 2016, Pages

  Li, Yonghui ^a   Akesson, Benny ^b   Lampka, Kai ^c   Goossens, Kees ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b INSTITUTO SUPERIOR DE ENGENHARIA DO PORTO   (Portugal)

^c UPPSALA UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLERS; DYNAMIC RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; SCHEDULING;

COMMAND SCHEDULING; DIFFERENT MECHANISMS; MEMORY CONTROLLER; MODEL AND ANALYSIS; MODELING AND VERIFICATIONS; MULTI-CORE SYSTEMS; TIMING CONSTRAINTS; WORST CASE RESPONSE TIME;

MODEL CHECKING;

EID: 84971215721     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2016.7461341     Document Type: Conference Paper

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