Dual threshold voltage domino logic

European Solid-State Circuits Conference

Volumn , Issue , 1999, Pages 118-121

  Kao, James ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOMINO LOGIC; DUAL THRESHOLD VOLTAGE; PERFORMANCE PENALTIES; STAND-BY LEAKAGE; TRANSISTOR SIZING;

EID: 84893746207     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, " IEEE JSSC, vol. 30, no. 8, pp. 847-854, August 1995.
2. J. Kao, A. Chandrakasan, D. Antoniadis, "Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology, " 34th Design Automation Conference, pp. 409-414, June 1997.
3. J. Kao, S. Narendra, A. Chandrakasan, "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns, " 35th Design Automation Conference, pp. 495-500, June 1998.
4. W. Lee, et al., "A 1V DSP for Wireless Communications, " ISSCC, pp. 92-93, Feb., 1997.
5. L. Wei, Z. Chen, M. Johnson, K. Roy, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits, " 35th Design Automation Conference, pp. 489-494, June 1998.
6. N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design, " Addison-Wesley, Reading MA., pp. 301-302, 1993.
7. Kerry Bernstein, IBM Microelectronics, Essex Junction, Vt, personal communication.