Energy-delay efficient data memory subsystems

IEEE Signal Processing Magazine

Volumn 22, Issue 3, 2005, Pages 23-37

  Ramachandran, Anand ^a   Jacome, Margarida F ^b  

^a INTEL CORPORATION   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENCY CONTROL; DATA TRANSFER; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; GENERAL PURPOSE COMPUTERS; SYNCHRONIZATION;

DATA MEMORY SUBSYSTEMS; EMBEDDED MEDIA PROCESSING; SYNCHRONIZATION CONSTRAINTS;

DATA STORAGE EQUIPMENT;

EID: 85032751806     PISSN: 10535888     EISSN: None     Source Type: Journal    
DOI: 10.1109/MSP.2005.1425895     Document Type: Article

References (27)

1. J. Fritts, W. Wolf, and B. Liu, "Understanding multimedia application characteristics for designing programmable media processors," in Proc. SPIE Photonics West, Media Processors, 1999, pp. 2-13.
2. C.J. Hughes, J. Srinivasan, and S.V. Adve, "Saving energy with architectural and frequency adaptations for multimedia applications," in Proc. Int. Symp. Microarchitecture, 2001, pp. 254-265.
3. B. Khailany, W.J. Dally, S. Rixner, U.J. Kapasi, P. Mattson, J. Namkoong, J.D. Owens, B. Towles, and A. Chang, "Imagine: Media processing with streams," IEEE Micro, vol. 21, no. 2, 2001, pp. 35-46.
4. P. Ranganathan, S. Adve, and N.P. Jouppi, "Performance of image and video processing with general-purpose processors and media ISA extensions," in Proc. Int. Symp. Computer Architecture, 1999, pp. 124-135.
5. P. Grun, N. Dutt, and A. Nicolau. Memory Architecture Exploration for Programmable Embedded Systems. Norwell, MA: Kluwer, 2003.
6. P.R. Panda, N.D. Dutt, and A. Nicolau, Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration. Norwell, MA: Kluwer, 1999.
7. V. Delaluz, A, Sivassubramaniam, M. Kandemir, N. Vijaykrishnan, and M.J. Irwin, "Scheduler-based DRAM energy management," in Proc. Design Automation Conf., 2002, pp. 697-702.
8. X. Fan, C.S Fills, and A.R. Lebeck, "Memory controller policies for DRAM power management," in Proc. Int. Symp. Low Power Electronics and Designs, 2001, pp. 129-134.
9. A. Ramachandran and M.F. Jacome, "Xtream-Fit: An energy-delay efficient data memory sub-system for embedded media processing" in Proc. Design Automation Conf., 2003, pp. 137-142
10. C. Lee, M. Potkonjak, and W.H. mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. Int. Symp. Microarchitecture, 1997 pp. 330-335.
11. C.J. Hughes, P. Kaul, S.V. Adve, R. Jain, C. Park, and J. Srinivasan, "Variability in the excecution of multimedia applications and implications for architecture," in Proc. Int. Symp. Computer Architecture, 2001, pp. 254-265.
12. S. Rixner, W.J. Dally, U.J. Kapasi, P.R. Mattson, and J.D. Owens, "Memory access scheduling," in Proc. Int. Symp. Computer Architecture, 2000, pp. 128-138.
13. M. Kandemir, J. Ramanujam, M. Irwin, N. Vijaykrishanan, I. Kadayif, and A. Parikh, "Dynamic management of scratch-pad memory space," in Proc. Design Automation Conf., 2001, pp. 690-695.
14. P.R. Panda, N.D. Dutt, and A. Nicolau, "Efficient utilization of scratch-pad memory in embedded processor applications," in Proc. European Design and Test Conf., 1997, pp. 7-11.
15. O.S. Unsal, R. Ashok, I. Koren, C.M. Krishna, and C.A. Moritz, "Cool-cache for hot multimedia," in Proc. Int. Symp. Microarchtecture, 2001, pp. 274-283.
16. O.S. Unsal, Z. Wang, I. Koren, C.M. Krishna, and C.A. Moritz, "On memory behavior of scalars in embedded multimedia systems," in Proc. Workshops Memory Performance Issues, 2001.
17. 128 MBit Micron Mobile SDRAM Data Sheet, Micron Technology Inc. [Online]. Available: http://www.micron.com/
18. 128 MBit Samsung Mobile SDRAM Data Sheet, Samsung Electronics [Online]. Available: http://www.samsung.com/
19. R. Gonzalez, B. Gordon, and M. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, 1997.
20. F. Catthoor, S. Wuytack, E. DeGreef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design. Norwell, MA: Kluwer, 1998.
21. S. Dutta, W. Wolf, and A. Wolfe, "A methodology to evaluate memory architectrue design tradeoffs for vidos signal processors," IEEE Trans. Circuits Syst. Video Technol.,vol. 8, no. 1, pp. 36-53, 1998.
22. D.M. Tullsen, J. Eggers, and H.M. levy, "Simultaneous multithreading: maximizing on-chip parallelism," in Proc. Int. Symp. Computer Architecture, 1995, pp. 392-403.
23. D. Madon, E. Sanchez, and S. Monnier, "A study of a simultaneous multithreaded processor implementation," in Proc. Euro. Conf. Parallel Processing, 1999, pp. 716-726.
24. D. Burger, T.M. Austin, and S. Bennett, "Evaluating future microprocessors: The simpleScalar tool set. Technical report," Computer Sciences Dept., Univ. of Wisconsin-Madison, 1996.
25. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: Exploiting generational behaviour to reduce cache leakage power," in Proc. Int. Symp. Computer Archtecture, 2001, pp. 240-251.
26. H. Zhou, M.C. Toburen, E. Rotenberg, and T.M. Conte, "Adaptive mode control: A static-power-efficient cache design," in Proc. Int. Conf. Parallel Archtecutre and Compliation Techniques, 2001, pp. 61-72.
27. T. Wiangtong, P.Y.K. Cheung, and W. Luk, "Hardware/software codesign," IEEE Signal Processing Mag., vol. 22, pp. 14-22, May 2005.