A methodology to evaluate memory architecture design tradeoffs for video signal processors

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 8, Issue 1, 1998, Pages 36-53

  Dutta, Santanu ^a   Wolf, Wayne ^b,c   Wolfe, Andrew ^b,c  

^a NXP SEMICONDUCTORS   (Netherlands)

^b Princeton University   (United States)

^c IEEE

Author keywords

Circuit simulation; Hierarchical memory architecture; Memory bank conflict; Multiport memory; Multistage interconnection network

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS;

DISCRETE COSINE TRANSFORMS (DCT);

VIDEO SIGNAL PROCESSING;

EID: 0031999304     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.660828     Document Type: Review

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