A Chip-level Redundant Threading (CRT) scheme for shared-memory protection

2016 International Conference on High Performance Computing and Simulation, HPCS 2016

Volumn , Issue , 2016, Pages 116-124

  Koser, Erol ^a   Berthold, Korbinian ^a   Kumar Pujari, Ravi ^a   Stechele, Walter ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FAULT DETECTION; RECONFIGURABLE HARDWARE;

FUNCTIONAL SAFETY; MEMORY CONTROLLER; MEMORY TECHNOLOGY; MULTICORE ARCHITECTURES; PERFORMANCE DEGRADATION; PERFORMANCE PENALTIES; PROCESSING ELEMENTS; SHARED COMPONENTS;

MEMORY ARCHITECTURE;

EID: 84991666141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCSim.2016.7568324     Document Type: Conference Paper

References (14)

1. R. Baumann, "Soft errors in advanced computer systems, " IEEE Design & Test of Computers, vol. 22, no. 3, pp. 258-266, May 2005.
2. T. J. Slegel, R. M. Averill, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. MacDougall, T. J. McPherson, J. A. Navarro, E. M. Schwarz, K. Shum, and C. F. Webb, "IBM's S/390 G5 microprocessor design, " IEEE Micro, vol. 19, no. 2, pp. 12-23, Mar. 1999.
3. M. D. Cin, W. Hohl, E. Michel, and A. Pataricza, "Error detection mechanisms for massively parallel multiprocessors, " in Proc. Euromicro Workshop Parallel and Distributed Processing, Jan. 1993, pp. 401-408.
4. K. Sundaramoorthy, Z. Purser, and E. Rotenburg, "Slipstream processors: improving both performance and fault tolerance, " in ACM SIGARCH Computer Architecture News, vol. 28, no. 5. ACM, 2000, pp. 257-268.
5. S. K. Reinhardt and S. S. Mukherjee, "Transient fault detection via simultaneous multithreading, " in Proc. 27th Int Computer Architecture Symp, Jun. 2000, pp. 25-36.
6. T. N. Vijaykumar, I. Pomeranz, and K. Cheng, "Transient-fault recovery using simultaneous multithreading, " in Proc. 29th Annual Int Computer Architecture Symp, 2002, pp. 87-98.
7. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt, "Detailed design and evaluation of redundant multi-threading alternatives, " in Proc. 29th Annual Int Computer Architecture Symp, 2002, pp. 99-110.
8. R. Gong, K. Dai, and Z. Wang, "Transient fault tolerance on chip multiprocessor based on dual and triple core redundancy, " in Proc. 14th IEEE Pacific Rim Int. Symp. Dependable Computing PRDC '08, Dec. 2008, pp. 273-280.
9. M. Gomaa, C. Scarbrough, T. N. Vijaykumar, and I. Pomeranz, "Transient-fault recovery for chip multiprocessors, " in Proc. 30th Annual Int Computer Architecture Symp, Jun. 2003, pp. 98-109.
10. C. LaFrieda, E. Ipek, J. F. Martinez, and R. Manohar, "Utilizing dynamically coupled cores to form a resilient chip multiprocessor, " in Proc. 37th Annual IEEE/IFIP Int. Conf. Dependable Systems and Networks (DSN'07), Jun. 2007, pp. 317-326.
11. A. Golander, S. Weiss, and R. Ronen, "DDMR: Dynamic and scalable dual modular redundancy with short validation intervals, " IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 65-68, Jul. 2008.
12. D. Sánchez, J. L. Aragón, and J. M. Garcia, "Adapting dynamic core coupling to a direct-network environment, " Proc. XIX Jornadas de Paralelismo, 2008.
13. J. Gaisler, E. Catovic, M. Isomaki, K. Glembo, and S. Habinc, "GRLIB IP core users manual, " Gaisler research, 2007.
14. J. Hennessy. Stanford baby benchmark suit. [Online]. Available: http: //classes. engineering. wustl. edu/cse465/docs/BCCExamples/stanford. c