-
1
-
-
0031635930
-
A coarse-grained FPGA architecture for high-performance fir filtering
-
Anderson, J., Sheth, S., Roy, K., 1998. A coarse-grained FPGA architecture for high-performance fir filtering. In Proceedings of 1998 ACM/SIGDA 6th International Symposium on Field Programming Gate Arrays. 234-243.
-
(1998)
Proceedings of 1998 ACM/SIGDA 6th International Symposium on Field Programming Gate Arrays.
, pp. 234-243
-
-
Anderson, J.1
Sheth, S.2
Roy, K.3
-
2
-
-
84893803869
-
Synthesis of application-specific highly efficient multimode systems for low-power applications
-
Chiou, L., Bhunia, S., Roy, K., 2003. Synthesis of application-specific highly efficient multimode systems for low-power applications. In IEEE Design, Automation and Test in Europe Conference.
-
(2003)
IEEE Design, Automation and Test in Europe Conference.
-
-
Chiou, L.1
Bhunia, S.2
Roy, K.3
-
3
-
-
0034855046
-
DSP datapath synthesis for low-power applications
-
Chiou, L., Muhammad, K., Roy, K., 2001a. DSP datapath synthesis for low-power applications. In IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 2, 1165-1168.
-
(2001)
IEEE International Conference on Acoustics, Speech, and Signal Processing
, vol.2
, pp. 1165-1168
-
-
Chiou, L.1
Muhammad, K.2
Roy, K.3
-
4
-
-
0034927706
-
Signal strength based switching activity modeling and estimation for dsp applications
-
Chiou, L., Muhammad, K., Roy, K., 2001b. Signal strength based switching activity modeling and estimation for dsp applications. VLSI Design. 233-243.
-
(2001)
VLSI Design.
, pp. 233-243
-
-
Chiou, L.1
Muhammad, K.2
Roy, K.3
-
5
-
-
0033718353
-
Multi-algorithm asip synthesis and power estimation for dsp applications
-
Cousin, J.-G., Sentieys, O., Chillet, D., 2000. Multi-algorithm asip synthesis and power estimation for dsp applications. International Symposium on Circuits and Systems. II. 621-624.
-
(2000)
International Symposium on Circuits and Systems.
, vol.II
, pp. 621-624
-
-
Cousin, J.-G.1
Sentieys, O.2
Chillet, D.3
-
7
-
-
0003558118
-
-
Kluwer Academic Publishers, Boston, MA
-
Gajski, D., Dutt, N., Wu, A., Ludwig, J., 1992. High-Level Synthesis. Kluwer Academic Publishers, Boston, MA.
-
(1992)
High-Level Synthesis.
-
-
Gajski, D.1
Dutt, N.2
Wu, A.3
Ludwig, J.4
-
10
-
-
0032023823
-
Behavioral-level synthesis of heterogeneous bisr reconfigurable ASIC's
-
Mar
-
Guerra, L., Potkonjak, M., Rabaey, J., 1998. Behavioral-level synthesis of heterogeneous bisr reconfigurable ASIC's. IEEE Trans. VLSI Syst. 6, 1 (Mar.), 158-167.
-
(1998)
IEEE Trans. VLSI Syst.
, vol.6
, Issue.1
, pp. 158-167
-
-
Guerra, L.1
Potkonjak, M.2
Rabaey, J.3
-
11
-
-
0036042405
-
Compiler-directed customization of asip cores
-
Gupta, T., Ko, R., Barua, R., 2002. Compiler-directed customization of asip cores. In Proceedings of 10th International Symposium on Hardware/Software Codesign. 97-102.
-
(2002)
Proceedings of 10th International Symposium on Hardware/Software Codesign.
, pp. 97-102
-
-
Gupta, T.1
Ko, R.2
Barua, R.3
-
12
-
-
0025535964
-
Data path allocation based on bipartite weighted matching
-
Huang, C.-Y., Chen, Y.-S., Lin, Y.-L., Hsu, Y.-C., 1990. Data path allocation based on bipartite weighted matching. In Proceedings of ACM/IEEE Design Automation Conference. 499-504.
-
(1990)
Proceedings of ACM/IEEE Design Automation Conference.
, pp. 499-504
-
-
Huang, C.-Y.1
Chen, Y.-S.2
Lin, Y.-L.3
Hsu, Y.-C.4
-
13
-
-
0343480503
-
Empirical evaluation of some high-level synthesis scheduling heuristics
-
Jain, R., Mujumdar, A., Sharma, A., Wang, H., 1991. Empirical evaluation of some high-level synthesis scheduling heuristics. In Proceedings of ACM/IEEE Design Automation Conference. 210-215.
-
(1991)
Proceedings of ACM/IEEE Design Automation Conference.
, pp. 210-215
-
-
Jain, R.1
Mujumdar, A.2
Sharma, A.3
Wang, H.4
-
14
-
-
0030717812
-
Synthesis of application specific programmable processors
-
Kim, K., Karri, R., Potkonjak, M., 1997. Synthesis of application specific programmable processors. 353-358.
-
(1997)
, pp. 353-358
-
-
Kim, K.1
Karri, R.2
Potkonjak, M.3
-
15
-
-
0003476270
-
-
Prentice-Hall, Englewood Cliffs, NJ
-
Lin, S., Daniel, J., Costello, J., 1983. Error Control Coding: Fundamentals and Applications. Prentice-Hall, Englewood Cliffs, NJ.
-
(1983)
Error Control Coding: Fundamentals and Applications.
-
-
Lin, S.1
Daniel, J.2
Costello, J.3
-
17
-
-
0029206334
-
High-level synthesis techniques for reducing the activity of functional units
-
Mussol, E., Cortadella, J., 1995. High-level synthesis techniques for reducing the activity of functional units. In International Symposium on Low Power Design. 99-104.
-
(1995)
International Symposium on Low Power Design.
, pp. 99-104
-
-
Mussol, E.1
Cortadella, J.2
-
19
-
-
0024682923
-
Force-directed scheduling for the behavioral synthesis of ASIC
-
June
-
Paulin, P., Knight, J., 1989. Force-directed scheduling for the behavioral synthesis of ASIC. IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. 8, 6 (June), 661-678.
-
(1989)
IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst.
, vol.8
, Issue.6
, pp. 661-678
-
-
Paulin, P.1
Knight, J.2
-
20
-
-
0003409584
-
-
Prentice Hall, Englewood Cliffs, NJ
-
Proakis, J. G., Manolakis, D. G., 1996. Digital Signal Processing: Principles, Algorithms and Applications. Prentice Hall, Englewood Cliffs, NJ.
-
(1996)
Digital Signal Processing: Principles, Algorithms and Applications.
-
-
Proakis, J.G.1
Manolakis, D.G.2
-
21
-
-
0036907239
-
Synthesis of custom processors based on extensible platforms
-
Sun, F., Ravi, S., Raghunathan, A., Jha, N., 2002. Synthesis of custom processors based on extensible platforms. In IEEE/ACM International Conference on Computer Aided Design. 641-648.
-
(2002)
IEEE/ACM International Conference on Computer Aided Design.
, pp. 641-648
-
-
Sun, F.1
Ravi, S.2
Raghunathan, A.3
Jha, N.4
-
25
-
-
0026992432
-
Area optimization of multifunction processing units
-
Va Der, Werf, A., Aerts, E., Peek, M., Vanmeerbergen, J., Lippens, P., Verhaegh, W., 1992. Area optimization of multifunction processing units. In International Conference on Computer Aided Design. 292-299.
-
(1992)
International Conference on Computer Aided Design.
, pp. 292-299
-
-
Va, D.1
Werf, A.2
Aerts, E.3
Peek, M.4
Vanmeerbergen, J.5
Lippens, P.6
Verhaegh, W.7
-
26
-
-
0033724033
-
A review of high-level synthesis for dynamically reconfigurable fpgas
-
Zhang, X., Ng, K. W., 2000. A review of high-level synthesis for dynamically reconfigurable fpgas. Microprocess. Microsyst. 24, 199-211.
-
(2000)
Microprocess. Microsyst.
, vol.24
, pp. 199-211
-
-
Zhang, X.1
Ng, K.W.2
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