Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 96-101

  Chiou, Lih Yih ^a   Bhunia, Swarup ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EFFICIENT SCHEDULING; LOW POWER APPLICATION; MULTIMEDIA APPLICATIONS; MULTIPLE CONFIGURATIONS; NOVEL DESIGN METHODOLOGY; PROGRAMMABLE SYSTEMS; RECONFIGURABLE PLAT-FORMS; RECONFIGURABLE SYSTEMS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA FLOW ANALYSIS; DATA FLOW GRAPHS; EXHIBITIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE HARDWARE;

STRUCTURAL DESIGN;

EID: 84893803869     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253593     Document Type: Conference Paper

References (10)

1. D. Gajski and N.Dutt and A. Wu, and J.T. Ludwig. High-Level Synthesis. Kluwer Academic Publishers, 1992
2. J. R. Anderson, S. Sheth, and K. Roy. A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. In Proceedings of 1998 ACM/SIGDA sixth International Symposium on Field Programming Gate Arrays, pages 234-243, 1998
3. G. D. Micheli. Synthesis and Optimization of Digital Circuits. McGRAW-HILL, 1994
4. X. Zhang and K. W. Ng. A review of High-Level Synthesis for Dynamically Reconfigurable FPGAs. Microprocessors and Microsystems, 24:199-211, 2000
5. L. M. Guerra, M. Potkonjak, and J. M. Rabaey. Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASIC?s. IEEE Trans. on VLSI Systems, 6(1):158-167, March 1998
6. C. Gebotys. ILP Model for Simultaneous Scheduling and Partitioning for Low Power System Mapping. Technical report, University of Waterloo, Department of Electrical and Computer Engineering, VLSI Group, April 1995
7. C.-Y. Huang, Y.-S. Chen, Y.-L. Lin, and Y.-C. Hsu. Data Path Allocation Based on Bipartite Weighted Matching. In Proceedings of ACM/IEEE Design Automation Conference, pages 499-504, June 1990
8. E. Mussol and J. Cortadella. High-Level Synthesis Techniques for Reducing the Activity of Functional Units. In International Symposium on Low Power Design, pages 99-104, April 1995
9. L.-Y. Chiou, K. Muhammad, and K. Roy. DSP Datapath Synthesis for Low-Power Applications. In IEEE International Conference on Acoustics, Speech, and Signal Processing, volume 2, pages 1165-1168, May 2001
10. L.-Y. Chiou, K. Muhammad, and K. Roy. Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. VLSI DESIGN, pages 233-243, Feb 2001