Power reduction for ASIPs: A case study

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2001, Pages 235-246

  Glökler, Tilman ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ELECTRIC POWER SUPPLIES TO APPARATUS; OPTIMIZATION; REDUCED INSTRUCTION SET COMPUTING;

APPLICATION SPECIFIC INSTRUCTION SET PROCESSORS; POWER OPTIMIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0035157415     PISSN: 15206130     EISSN: None     Source Type: Journal    
DOI: 10.1109/SIPS.2001.957352     Document Type: Article

References (16)

1. ASIP design methodologies: Survey and issues
2. PEAS-III: An ASIP design environment
3. MetaCore: An application-specific programmable DSP development system
4. Ultra-low-power domain-specific multimedia processors
5. Increasing the power efficiency of application specific instruction set processors using datapath optimization
6. Power efficient semi-automatic instruction encoding for application specific instruction set processors
7. High speed: Not the only way to exploit the intrinsic computational power of silicon
8. LISA - Machine description language for cycle-accurate models of programmable DSP architectures
9. A methodology for accurate performance evaluation in architecture exploration
10. Incorporating compiler feedback into the design of ASIPs
11. Retargetable code generation based on structural processor descriptions
12. Designing the low-power M•Core architecture, M•Core technology center