A memory-centric approach to enable timing-predictability within embedded many-core accelerators

CSI Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2015

Volumn , Issue , 2015, Pages

  Burgio, Paolo ^a   Marongiu, Andrea ^b   Valente, Paolo ^a   Bertogna, Marko ^a  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS;

COMMUNICATION RESOURCES; HETEROGENEOUS PLATFORMS; INDUSTRIAL SETTINGS; MANY-CORE ACCELERATORS; MULTI-CORE PLATFORMS; MULTIPLE INTERFERENCES; PARALLEL APPLICATION; WORST-CASE EXECUTION TIME ANALYSIS;

REAL TIME SYSTEMS;

EID: 84964826964     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTEST.2015.7369851     Document Type: Conference Paper

References (27)

1. Adapteva, Inc., "Epiphany-IV 64-core 28nm Microprocessor," [Online] http://www.adapteva.com/products/ silicon-devices/e64g401/, 2013.
2. L. Benini, E. Flamand, D. Fuin, and D. Melpignano, "P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator," in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, 2012, pp. 983-987.
3. Kalray Corporation, "Many-core Kalray MPPA," [Online] http://www.kalray.eu/, 2012.
4. NVIDIA, "Next Generation CUDA Compute Architecture: Fermi-WhitePaper," [Online] http://www.nvidia.fr/content/PDF/fermi-white-papers/ NVIDIA-Fermi-Compute-Architecture-Whitepaper.pdf, 2010.
5. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley, "A predictable execution model for COTS-based embedded systems," in Proceedings of the 17th IEEE International Real-Time and Embedded Technology and Applications Symposium, ser. RTAS '11, April 2011, pp. 269-279.
6. A. Marongiu and L. Benini, "An OpenMP compiler for efficient use of distributed scratchpad memory in MPSoCs," Computers, IEEE Transactions on, vol. 61, no. 2, pp. 222-236, Feb 2012.
7. L. Karam, I. AlKamal, A. Gatherer, G. Frantz, D. Anderson, and B. Evans, "Trends in multicore DSP platforms," Signal Processing Magazine, IEEE, vol. 26, no. 6, pp. 38-49, November 2009.
8. S. Chattopadhyay and A. Roychoudhury, "Static bus schedule aware scratchpad allocation in multiprocessors," SIGPLAN Not., vol. 46, no. 5, pp. 11-20, Apr. 2011. [Online]. Available: http://doi.acm.org/10.1145/2016603.1967680
9. I. Puaut and C. Pais, "Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison," in Design, Automation Test in Europe Conference Exhibition, 2007. DATE '07, April 2007, pp. 1-6.
10. B. Lickly, I. Liu, S. Kim, H. D. Patel, S. A. Edwards, and E. A. Lee, "Predictable programming on a precision timed architecture," in Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, ser. CASES '08. New York, NY, USA: ACM, 2008, pp. 137-146. [Online]. Available: http://doi.acm.org/10.1145/1450095.1450117
11. S. Wasly and R. Pellizzoni, "A dynamic scratchpad memory unit for predictable real-time embedded systems," in Real-Time Systems (ECRTS), 2013 25th Euromicro Conference on, July 2013.
12. R. Pellizzoni, B. Bui, M. Caccamo, and L. Sha, "Coscheduling of CPU and I/O transactions in COTS-based embedded systems," in Proceedings of the IEEE Real-Time Systems Symposium, Nov 2008, pp. 221-231.
13. A. Marongiu, P. Burgio, and L. Benini, "Fast and lightweight support for nested parallelism on cluster-based embedded manycores," in 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012, 2012, pp. 105-110.
14. Texas Instrument Inc., "The 66AK2H12 Keystone II Processor." [Online]. Available: http://www.ti.com/product/66AK2H12
15. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, "Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms," in Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, ser. RTAS '13. Washington, DC, USA: IEEE Computer Society, 2013, pp. 55-64.
16. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, "Memory access control in multiprocessor for real-time systems with mixed criticality," in Proceedings of the 24th Euromicro Conference on Real-Time Systems, ser. ECRTS '12. Washington, DC, USA: IEEE Computer Society, 2012, pp. 299-308.
17. J. Whitham and N. Audsley, "Implementing time-predictable load and store operations," in Proceedings of the Seventh ACM International Conference on Embedded Software, ser. EMSOFT '09. New York, NY, USA: ACM, 2009, pp. 265-274. [Online]. Available: http://doi.acm.org/10.1145/1629335.1629371
18. S. Bak, G. Yao, R. Pellizzoni, and M. Caccamo, "Memoryaware scheduling of multicore task sets for real-time systems," in Proceedings of the 18th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, ser. RTCSA '12, Aug 2012, pp. 300-309.
19. G. Yao, R. Pellizzoni, S. Bak, E. Betti, and M. Caccamo, "Memory-centric scheduling for multicore hard real-time systems," Real-Time Systems, vol. 48, no. 6, pp. 681-715, 2012. [Online]. Available: http://dx.doi.org/10.1007/s11241-012-9158-9
20. Kronos Group, "The OpenCL 1.1 Specifications," 2010. [Online]. Available: http://www.khronos.org/registry/cl/specs/opencl-1.1.pdf
21. "OpenMP Application Program Interface v4," 2011. [Online]. Available: http://www.openmp.org/mpdocuments/ OpenMP3.1.pdf
22. P. Burgio, G. Tagliavini, A. Marongiu, and L. Benini, "Enabling fine-grained OpenMP tasking on tightly-coupled shared memory clusters," in Design, Automation Test in Europe Conference Exhibition (DATE), 2013, 2013, pp. 1504-1509.
23. I. Puaut, "WCET-centric software-controlled instruction caches for hard real-time systems," in Real-Time Systems, 2006. 18th Euromicro Conference on, 2006, pp. 10 pp.-226.
24. A. Alhammad and R. Pellizzoni, "Time-predictable execution of multithreaded applications on multicore systems," in Proceedings of Design, Automation and Test in Europe, ser. DATE '14, Mar 2014.
25. J. Sancho and D. Kerbyson, "Analysis of double buffering on two different multicore architectures: Quad-core opteron and the cellbe," in Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on, April 2008, pp. 1-12.
26. P. Puschner and A. Schedl, "Computing maximum task execution times - a graph-based approach," Real-Time Systems, vol. 13, no. 1, pp. 67-91, 1997.
27. V. Nélis, P. M. Yomsi, and L. M. Pinho, "Methodologies for the WCET Analysis of Parallel Applications on Many-core Architectures," in 18th Euromicro Conference on Digital System Design, DSD 2015, August 2015.