Time-predictable execution of multithreaded applications on multicore systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Alhammad, Ahmed ^a,b   Pellizzoni, Rodolfo ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

^b KING SAUD UNIVERSITY   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

SCHEDULING ALGORITHMS;

APPLICATION THREADS; EXPERIMENTAL EVALUATION; MULTI-CORE SYSTEMS; MULTI-THREADED APPLICATION; NAS PARALLEL BENCHMARKS; REAL-TIME APPLICATION; TIMING ANALYSIS; WORST-CASE PERFORMANCE;

BENCHMARKING;

EID: 84903848201     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.042     Document Type: Conference Paper

References (16)

1. H.-M. Huang, T. Tidwell, C. Gill, C. Lu, X. Gao, and S. Dyke, "Cyberphysical systems for real-time hybrid structural testing: a case study," in Proc. Int. Conf. Cyber-Physical Systems. ACM, 2010, pp. 69-78.
2. A. Kurdila, M. Nechyba, R. Prazenica, W. Dahmen, P. Binev, R. De-Vore, and R. Sharpley, "Vision-based control of micro-air-vehicles: Progress and problems in estimation," in Proc. Decision and Control, vol. 2. IEEE, 2004, pp. 1635-1642.
3. K. Lakshmanan, S. Kato, and R. R. Rajkumar, "Scheduling parallel real-time tasks on multi-core processors," in Proc. RTSS. IEEE, 2010, pp. 259-268.
4. A. Saifullah, K. Agrawal, C. Lu, and C. Gill, "Multi-core real-time scheduling for generalized parallel task models," in Proc. RTSS. IEEE, 2011, pp. 217-226.
5. R. Pellizzoni, A. Schranzhofery, J.-J. Cheny, M. Caccamo, and L. Thieley, "Worst case delay analysis for memory interference in multicore systems," in Proc. DATE. IEEE, 2010, pp. 741-746.
6. H. Jin, M. Frumkin, and J. Yan, "The openmp implementation of nas parallel benchmarks and its performance," Technical Report NAS-99-011, NASA Ames Research Center, Tech. Rep., 1999.
7. F. Boniol, H. Casśe, E. Noulard, and C. Pagetti, "Deterministic execution model on COTS hardware," Architecture of Computing, pp. 98-110, 2012.
8. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley, "A predictable execution model for cots-based embedded systems," in Proc. RTAS. IEEE, 2011, pp. 269-279.
9. G. Yao, R. Pellizzoni, S. Bak, E. Betti, and M. Caccamo, "Memorycentric scheduling for multicore hard real-time systems," Real-Time Systems, vol. 48, no. 6, pp. 681-715, 2012.
10. D. Lea, "A java fork/join framework," in Proc. Conf. Java Grande. ACM, 2000, pp. 36-43.
11. IA-32 Architectures Software Developers Manual, Volume 3a ed., Intel, 2011.
12. S. Udayakumaran, A. Dominguez, and R. Barua, "Dynamic allocation for scratch-pad memory using compile-time decisions," ACM Transactions on Embedded Computing Systems, vol. 5, no. 2, pp. 472-511, May 2006.
13. R. Mancuso, R. Dudko, E. Betti, M. Cesati, M. Caccamo, and R. Pellizzoni, "Real-time cache management framework for multi-core architectures," in Proc. RTAS. IEEE, 2013, pp. 45-54.
14. A. Darte, Y. P. Robert, F. Vivien, and F. Vivien, Scheduling and automatic Parallelization. Springer, 2000.
15. P. Radojković, V. Cakarević, M. Moretó, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero, "Optimal task assignment in multithreaded processors: a statistical approach," in Proc. ASPLOS, 2012, pp. 235-248.
16. M. Bach, M. Charney, R. Cohn, E. Demikhovsky, T. Devor, K. Hazelwood, A. Jaleel, C.-K. Luk, G. Lyons, H. Patil et al., "Analyzing parallel programs with pin," Computer, vol. 43, no. 3, pp. 34-41, 2010.