A multi-PLL clock distribution architecture for gigascale integration

Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001

Volumn , Issue , 2001, Pages 30-35

  Saint Laurent, M ^a   Swaminathan, M ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; DESIGN FOR TESTABILITY; PHASE LOCKED LOOPS;

ALTERNATIVE SOLUTIONS; CLOCK DISTRIBUTION; CLOCK-DISTRIBUTION PROBLEMS; DIGITAL FEEDBACK; GIGASCALE INTEGRATION; PHASELOCKED LOOP (PLLS); PROPOSED ARCHITECTURES; SEMI-DISTRIBUTED;

NETWORK ARCHITECTURE;

EID: 84964545107     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2001.923136     Document Type: Conference Paper

References (11)

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