A digitally adjustable resistor for path delay characterization in high-frequency microprocessors

2001 Southwest Symposium on Mixed-Signal Design, SSMSD 2001

Volumn , Issue , 2001, Pages 61-64

  Saint Laurent, M ^a   Swaminathan, M ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS;

CONTROL BITS; FABRICATION TECHNOLOGIES; HIGH FREQUENCY HF; PATH DELAY CHARACTERIZATION; SILICON DEBUG; VARIABLE DELAYS;

RESISTORS;

EID: 84963820976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2001.914938     Document Type: Conference Paper

References (5)

1. U. Desai et al., "Itanium™ Processor Clock Design", International Symposium on Physical Design, 2000, pp. 94-98.
2. T. J. Gabara, and S. C. Knauer, "Digitally Adjustable Resistors in CMOS for High-Performance Applications", IEEE Journal of Solid-State Circuits, August 1992, pp. 1176-1185.
3. G. Geannopoulos, and X. Dai, "An Adaptive Digital Deskewing Circuit for Clock Distribution Networks", IEEE International Solid-State Circuits Conference, 1998, pp. 400-401.
4. H. Noda et al., "An On-Chip Clock-Adjusting Circuit with Sub-100-ps Resolution for a High-Speed DRAM Interface", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, August 2000, pp. 771-775.
5. M. Saint-Laurent, and G. P. Muyshondt, "A Digitally Controlled Oscillator Constructed Using Adjustable Resistors", IEEE Southwest Symposium on Mixed-Signal Design, 2001.