Clock distribution network for microprocessors

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 184-187

  Klisnick, A ^a   Kuba, J ^a,i   Ros, D ^a   Carillon, A ^a   Jamelot, G ^a   Smith, R ^a,j   Strati, F ^b   Tallents, G J ^b   Keenan, R ^c   Topping, S J ^c   Lewis, C L S ^c   Nickles, P ^d   Janulewicz, K A ^d   Bortolotto, F ^d   Neely, D ^e   Clarke, R ^e   Collier, J ^e   MacPhee, A G ^e   Chenais Popovics, C ^f   Chanteloup, J C ^f   Joyeux, D ^g   Phalippou, D ^g   Daido, H ^h   Tang, H ^h   more..

^a UNIVERSITÉ PARIS SACLAY   (France)

^b UNIVERSITY OF YORK   (United Kingdom)

^c QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^d MAX BORN INSTITUT   (Germany)

^e RUTHERFORD APPLETON LABORATORY   (United Kingdom)

^f ECOLE POLYTECHNIQUE   (France)

^g CNRS   (France)

^h JAPAN ATOMIC ENERGY AGENCY   (Japan)

ⁱ CZECH TECHNICAL UNIVERSITY IN PRAGUE   (Czech Republic)

^j LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; ELECTRIC INDUCTORS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; RESISTORS; TUNING;

CLOCK DISTRIBUTION NETWORKS;

TIMING CIRCUITS;

EID: 0033719722     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (0)