Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules

IEEE Micro

Volumn 36, Issue 1, 2016, Pages 24-34

  Asghari Moghaddam, Hadi ^a   Farmahini Farahani, Amin ^a   Morrow, Katherine ^b   Ahn, Jung Ho ^c   Kim, Nam Sung ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c Seoul National University   (South Korea)

Author keywords

accelerator; die stacking; DRAM; near data processing

Indexed keywords

DATA HANDLING; DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; MEMORY ARCHITECTURE; PARTICLE ACCELERATORS; THREE DIMENSIONAL INTEGRATED CIRCUITS;

BASELINE SYSTEMS; DIE STACKING; HETEROGENEOUS PROCESSING; MEMORY MODULES; PROCESS DATA; PROCESSOR MEMORY; SYSTEM ENERGY CONSUMPTION; TECHNOLOGY SCALING;

COMPUTER ARCHITECTURE;

EID: 84963766471     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2016.8     Document Type: Article

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