MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 23, Issue 10, 2015, Pages 2332-2336

  Saiz Adalid, Luis J ^a   Reviriego, Pedro ^b   Gil, Pedro ^a   Pontarelli, Salvatore ^c   Maestro, Juan Antonio ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

^c CNIT   (Italy)

Author keywords

Burst error correction codes (ECCs); EECs; memory; SEC DAEC; SEC DAEC TAEC; single error correction double error detection (SEC DED)

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CODES (SYMBOLS); ERROR CORRECTION; RADIATION HARDENING; REDUNDANCY; SEMICONDUCTOR STORAGE;

DECODER COMPLEXITY; ELECTRONIC SYSTEMS; ERROR CORRECTION CODES (ECCS); MULTIPLE CELL UPSET; SEMICONDUCTOR MEMORY; SINGLE ERROR CORRECTIONS; STAND-ALONE DEVICES; STATIC RANDOM ACCESS MEMORY;

STATIC RANDOM ACCESS STORAGE;

EID: 84959560502     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2014.2357476     Document Type: Article

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