New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011

Volumn , Issue , 2011, Pages 254-259

  Ming, Zhu ^a   Yi, Xiao Li ^a   Wei, Luo Hong ^b  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

^b Natl Key Lab of Sci and Technol on Reliability Phys and Applic Technol of Elec Component   (China)

Author keywords

MBUs; memory; memory reliability; SEC DED DAEC codes

Indexed keywords

BCH CODE; BIT-ERRORS; HARDWARE OVERHEADS; HARDWARE REDUNDANCY; MATHEMATICS MODEL; MBUS; MEMORY; MEMORY RELIABILITY; MEMORY SYSTEMS; MULTIPLE BIT UPSET; NOISE SOURCE; SEC-DED-DAEC CODES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIT ERROR RATE; CODES (SYMBOLS); ERROR CORRECTION; PROGRAMMABLE LOGIC CONTROLLERS; REDUNDANCY;

ERROR DETECTION;

EID: 83755172106     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISoC.2011.6081647     Document Type: Conference Paper

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