Low-cost single error correction multiple adjacent error correction codes

Electronics Letters

Volumn 48, Issue 23, 2012, Pages 1470-1472

  Reviriego, P ^a   Pontarelli, S ^b   Maestro, J A ^a   Ottavi, M ^b  

^a UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

^b UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ADJACENT BITS; BIT-ERRORS; ERROR CORRECTION CODES; LOW AREA; PROTECTION TECHNIQUES; SOFT ERROR;

DELAY CIRCUITS; FLIP FLOP CIRCUITS;

ERROR CORRECTION;

EID: 84868678998     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2012.3270     Document Type: Article

References (5)

1. Nicolaidis, M.: ' Design for soft error mitigation ', IEEE Trans. Device Mater. Reliab., 2005, 5, (3), p. 405-418 10.1109/TDMR.2005.855790 1530-4388
2. Ibe, E., Taniguchi, H., Yahagi, Y., Shimbo, K., and Toba, T.: ' Impact of scaling on neutron-induced soft error rate in SRAMs from a 250nm to a 22nm design rule ', IEEE Trans. Electron Devices, 2010, 57, (7), p. 1527-1538 10.1109/TED.2010.2047907 0018-9383
3. Satoh, S., Tosaka, Y., and Wender, S.A.: ' Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAMs ', IEEE Electron Device Lett., 2000, 21, (6), p. 310-312 10.1109/55.843160 0741-3106
4. Dutta, A., and Touba, N.A.: ' Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code ', 25th, IEEE VLSI Test Symp., Berkeley, CA, USA, 2007, p. 349-354
5. Stine, J.E.: et al. ' FreePDK: an open-source variation-aware design kit ', Proc. IEEE Int. Conf. Microelectronic Systems Education, (MSE'07), San Diego, CA, USA, June, 2007, p. 173-174