Value-profile guided stride prefetching for irregular code

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2304, Issue , 2002, Pages 307-324

  Wu, Youfeng ^a   Serrano, Mauricio ^a   Krishnaiyer, Rakesh ^a   Li, Wei ^a   Fang, Jesse ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLASSIFICATION (OF INFORMATION); INTEGER PROGRAMMING;

COMPILER TECHNIQUES; IRREGULAR PROGRAMS; LOAD CLASSIFICATION; MEMORY LOCATIONS; MEMORY OPERATIONS; PERFORMANCE GAIN; PROFILE DATA SET; STRIDE PREFETCHING;

PROGRAM COMPILERS;

EID: 84959039776     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45937-5_22     Document Type: Conference Paper

References (25)

1. Ball, T. and J. Larus, "Optimally profiling and tracing programs," ACM Transactions on Programming Languages and Systems, 16(3): 1319-1360, July 1994.
2. Calder, B., P. Feller, and A. Eustance. "Value Profiling," MICRO30, Dec. 1997.
3. Callahan, D., K. Kennedy, and A. Porterfield. "Software Prefetching", ASPLOS4, 1991, 40-52.
4. Collins, J., H. Wang, H. Christopher, D. Tullsen, C. J. Hughes, Y. F. Lee, D. Lavery and J. Shen, "Speculative Pre-computation: Long-range Prefetching of Delinquent Loads," ISCA28, 2001.
5. Dahlgren, F., Stenstrom, P., "Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors", IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 4, April 1996.
6. Doshi, G., R. Krishnaiyer, and K. Muthukumar. "Optimizing Software Data Prefetches with Rotating Registers", PACT 2001.
7. Farkas, K., P. Chow, N. Jouppi, and Z. Vranesic, "Memory-system design considerations for dynamically-scheduled processors," ISCA24, June 1997.
8. Huang, Xianglong, Zhenlin Wang, and K.S. McKinley. "Compiling for the Impulse memory controller," PACT 2001. Pages: 141-150
9. Intel Corp, "Benchmarks: Intel® Itanium™ based systems," http://www.intel.com/eBusiness/products/ia64/overview/bm012101.htm.
10. Intel Corp, Intel® Itanium™ Processor Hardware Developer™s Manual, 2000. http://developer.intel.com/design/ia-64/manuals.htm.
11. Jouppi, N., "Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers," ISCA17, May 1990
12. Karlsson, M., F. Dahlgren, and P. Stenstrom. "A Prefetching Technique for Irregular Accesses to Linked Data Structures," HPCA6, January. 2000
13. Lipasti, M.H., W.J. Schmidt, S.R. Kunkel, and R.R. Roediger, "SPAID: Software Prefetching in Pointer and Call Intensive Environments", MICRO28, Nov 1995, 231-236.
14. Luk, C., "Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors," ISCA28, 2001.
15. Luk, C.K. and T.C. Mowry, "Compiler-Based Prefetching for Recursive Data Structures," ASPLOS7, September 1996, 222-233.
16. Mahlke, S.A., D.C. Lin, W.Y. Chen, R.E. Hank, and R.A. Bringmann. "Effective Compiler Support for Predicated Execution Using Hyperblock," MICRO25, Dec. 1992, pp 45-54.
17. Mowry, T.C., M.S. Lam, and A. Gupta. "Design and Evaluation of a Compiler Algorithm for Prefetching," ASPLOS5, October 1992, 62-73.
18. Palacharla, S. and R. Kessler, "Evaluating stream buffers as secondary cache replacement," ISCA21, April 1994.
19. Roth, A., and G. Sohi. "Effective Jump-Pointer Prefetching for linked data structures," ISCA26, June 1999, 111-121.
20. Santhanam, V., E. Gornish, and W. Hsu, "Data Prefetching on the HP PA-8000," ISCA24, June 1997, 264-273.
21. Sherwood, T., S. Sair, B. Calder, "Predictor-Directed Stream Buffers," MICRO33, Dec. 2000.
22. Standard Performance Evaluation Corporation, "All SPEC CFP2000 Results Published by SPEC," http://www.spec.org/osg/cpu2000/results/res2001q2/cpu2000-20010522-00663.html, 2001.
23. Stoutchinin, A., J. N. Amaral, G. Gao, J. Dehnert, S. Jain, and A. Douillet "Speculative Prefetching of Induction Pointers," CC 2001, April, 2001. Also in LNCS 2207, pp 289-303, 2001.
24. Wiel, V., S.P., Lilja, D.J. "When caches aren’t enough: data prefetching techniques," Computer, Volume: 30 Issue: 7, July 1997, Page(s): 23-30
25. Zilles, C. and G. Sohi, "Execution-based Prediction Using Speculative Slices," ISCA28, 2001.