Evaluation of hardware-based stride and sequential prefetching in shared-memory multiprocessors

IEEE Transactions on Parallel and Distributed Systems

Volumn 7, Issue 4, 1996, Pages 385-398

  Dahlgren, Fredrik ^a,b   Stenström, Per ^a,c  

^a IEEE

^b LUND UNIVERSITY   (Sweden)

^c CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

Hardware controlled prefetching; Latency tolerance; Performance evaluation; Relaxed memory consistency; Shared memory multiprocessors

Indexed keywords

BUFFER STORAGE; CLASSIFICATION (OF INFORMATION); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA PROCESSING; MICROCOMPUTERS; PERFORMANCE;

HARDWARE CONTROLLED PREFETCHING; LATENCY TOLERANCE; RELAXED MEMORY CONSISTENCY; SHARED MEMORY MULTIPROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 0030121135     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.494633     Document Type: Review

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