Speculative prefetching of induction pointers

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2027, Issue , 2001, Pages 289-303

  Stoutchinin, Artour ^a   Amaral, José Nelson ^b   Gao, Guang R ^c   Dehnert, James C ^d   Jain, Suneel ^e   Douillet, Alban ^c  

^a STMICROELECTRONICS   (France)

^b UNIVERSITY OF ALBERTA   (Canada)

^c UNIVERSITY OF DELAWARE   (United States)

^d Transmeta Corporation   (United States)

^e HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; DATA FLOW ANALYSIS; FLOW GRAPHS; ITERATIVE METHODS; PROGRAM COMPILERS;

AUTOMATIC APPROACHES; BENCHMARK PROGRAMS; CONTROL FLOW GRAPHS; ESTIMATION ALGORITHM; INTERFERENCE GRAPHS; MEMORY BANDWIDTHS; POINTER PREFETCHING; PROCESSOR RESOURCES;

CACHE MEMORY;

EID: 84958984518     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45306-7_20     Document Type: Conference Paper

References (20)

1. T. F. Chen and J. L. Baer. Effective hardware-based data prefetching for highperformance processors. IEEE Transactions on Computers, 44:609-623, May 1995.
2. T. M. Chilimbi, M. D. Hill, and J. R. Larus. Making pointer-based data structures cache conscious. Computer, 33(12):67-74, December 2000.
3. F. Chow, S. Chan, R. Kennedy, S-M Liu, R. Lo, and Peng Tu. A new algorithm for partial redundancy elimination based on SSA form. In International Conference on Programming Languages Design and Implementation, pages 273-286, 1997.
4. T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. MIT Press; McGraw-Hill Book Company, Cambridge, Massachusetts; New York, New York, 1990.
5. J. C. Dehnert and R. A. Towle. Compiling for the cydra 5. The Journal of Supercomputing, 7:181-227, May 1993.
6. J. Fu and J. Patel. Stride directed prefetching in scalar processors. In International Symposium on Microarchitecture, pages 102-110, 1992.
7. J. Gonzales and A. Gonzales. Speculative execution via address prediction and data prefetching. In International Conference on Supercomputing, pages 196-203, 1997.
8. M. Lipasti, W. Schmidt, S. Kunkel, and R. Roediger. SPAID: Software prefetching in pointerand call-intensive environments. In International Symposium on Microarchitecture, pages 231-236, 1995.
9. C. K. Luk and T. Mowry. Compiler based prefetching for recursive data structures. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222-233, 1996.
10. S. Mantripragada, S. Jain, and J. Dehnert. A new framework for integrated global local scheduling. In Conference on Parallel Architectures and Compilation Techniques, pages 167-174, Paris, France, October 1998.
11. S. Mehrotra. Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation. PhD thesis, University of Illinois at Urbana-Champaign, 1996.
12. T. Mowry. Tolerating Latency Through Software-Controlled Data Prefetching. PhD thesis, Stanford University, 1994.
13. T. Mowry and C. K. Luk. Predicting data cache misses in non-numeric applications through correlation pro_ling. In International Symposium on Microarchitecture, pages 314-320, 1997.
14. T. Ozawa, Y. Kimura, and S. Nishizaki. Cache miss heuristics and preloading techniques for general-purpose programs. In International Symposium on Microarchitecture, pages 243-248, 1995.
15. B. Rau. Iterative modulo scheduling. Technical Report HPL-94-115, HP Laboratories, 1995.
16. A. Roth, A. Moshovos, and G. Sohi. Dependence based prefetching for linked data structures. In International Conference on Architectural Support for Programming Languages and Operating Systems, pages 115-126, 1998.
17. J. Ruttenberg, G. R. Gao, A. Stouchinin, and W. Lichtenstein. Software pipelining showdown: Optimal vs. heuristic methods in a production compiler. In International Conference on Programming Languages Design and Implementation, pages 1-11, Philadelphia, PA, May 1996.
18. C. Selvidge. Compilation-Based Prefetching for Memory Latency Tolerance. PhD thesis, MIT, 1992.
19. A. Stoutchinin, J. N. Amaral, G. R. Gao, J. Dehnert, and S. Jain. Automatic prefetching of induction pointers for software pipelining. Technical Report 37, November 1999.
20. R. Tarjan. Enumeration of the elementary circuits of a directed graph. SIAM Journal on Computing, 2(3):211-216, September 1973.