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Volumn 07-10-October-2012, Issue , 2015, Pages 94-98

GMS: Generic memristive structure for non-volatile FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; DATA STORAGE EQUIPMENT; DIGITAL STORAGE; PROGRAMMABLE LOGIC CONTROLLERS; RECONFIGURABLE HARDWARE; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

EID: 84959020283     PISSN: 23248432     EISSN: 23248440     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2012.7332083     Document Type: Conference Paper
Times cited : (4)

References (16)
  • 1
    • 55449122987 scopus 로고    scopus 로고
    • Overview of candidate device technologies for storage-class-memory
    • G.W. Burr et al., "Overview of candidate device technologies for storage-class-memory," IBM J. R&D, 52(4/5), 2008.
    • (2008) IBM J. R&D , vol.52 , Issue.4-5
    • Burr, G.W.1
  • 2
    • 84871832916 scopus 로고    scopus 로고
    • Challenges and Opportunities for HfOx Based Resistive Random Access Memory
    • Y.S. Chen et al., "Challenges and Opportunities for HfOx Based Resistive Random Access Memory," IEDM Tech. Dig., 2011.
    • (2011) IEDM Tech. Dig.
    • Chen, Y.S.1
  • 3
    • 79955726402 scopus 로고    scopus 로고
    • A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability
    • S.-S. Sheu et al., "A 4Mb Embedded SLC Resistive-RAM Macro with 7.2ns Read-Write Random-Access Time and 160ns MLC-Access Capability," ISSCC Tech. Dig., 2011.
    • (2011) ISSCC Tech. Dig.
    • Sheu, S.-S.1
  • 4
    • 33846603234 scopus 로고    scopus 로고
    • Performance Benefits of Monolithically Stacked 3-D FPGA
    • M. Lin et al., "Performance Benefits of Monolithically Stacked 3-D FPGA," IEEE TCAD, 26(2), 2007.
    • (2007) IEEE TCAD , vol.26 , Issue.2
    • Lin, M.1
  • 6
    • 84882180564 scopus 로고    scopus 로고
    • Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation
    • K. J. Han et al., "Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation," IEEE CICC, 2007.
    • (2007) IEEE CICC
    • Han, K.J.1
  • 7
    • 84860673822 scopus 로고    scopus 로고
    • Nonvolatile 3D-FPGA With Monolithically Stacked RRAM-Based Configuration Memory
    • Y.Y. Liauw et al., "Nonvolatile 3D-FPGA With Monolithically Stacked RRAM-Based Configuration Memory," ISSCC Tech. Dig., 2012.
    • (2012) ISSCC Tech. Dig.
    • Liauw, Y.Y.1
  • 8
    • 84855683107 scopus 로고    scopus 로고
    • Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics
    • D. Sacchetto et al., "Resistive Programmable Through Silicon Vias for Reconfigurable 3D Fabrics, IEEE TNANO, 11(1):8-11, 2012.
    • (2012) IEEE TNANO , vol.11 , Issue.1 , pp. 8-11
    • Sacchetto, D.1
  • 9
    • 79953082323 scopus 로고    scopus 로고
    • Emerging memory technologies for reconfigurable routing in FPGA architecture
    • P.-E. Gaillardon et al., "Emerging memory technologies for reconfigurable routing in FPGA architecture," ICECS Tech. Dig., 2010.
    • (2010) ICECS Tech. Dig.
    • Gaillardon, P.-E.1
  • 10
    • 80052913208 scopus 로고    scopus 로고
    • FPGA Based on Integration of CMOS and RRAM
    • Nov.
    • S. Tanachutiwat, M. Liu, and W. Wang, "FPGA Based on Integration of CMOS and RRAM," IEEE TVLSI, 19(11):2023-2032, Nov. 2011.
    • (2011) IEEE TVLSI , vol.19 , Issue.11 , pp. 2023-2032
    • Tanachutiwat, S.1    Liu, M.2    Wang, W.3
  • 11
    • 79961201211 scopus 로고    scopus 로고
    • mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
    • J. Cong and B. Xiao, "mrFPGA: A novel FPGA architecture with memristor-based reconfiguration," NANOARCH Tech. Dig., 2011.
    • (2011) NANOARCH Tech. Dig.
    • Cong, J.1    Xiao, B.2
  • 12
    • 77951622926 scopus 로고    scopus 로고
    • Complementary resistive switches for passive nanocrossbar memories
    • E. Linn, R. Rosezin, C. Kügeler and R. Waser, "Complementary resistive switches for passive nanocrossbar memories," Nature materials, 2010.
    • (2010) Nature Materials
    • Linn, E.1    Rosezin, R.2    Kügeler, C.3    Waser, R.4
  • 13
    • 84976237519 scopus 로고    scopus 로고
    • http://www.eda.ncsu.edu/wiki/FreePDK/
  • 15
    • 84959007015 scopus 로고    scopus 로고
    • ABC, Release 70930
    • Berkeley Logic Synthesis and Verification Group, ABC, Release 70930. http://www.eecs.berkeley.edu/~alanmi/abc/
  • 16
    • 79952957517 scopus 로고    scopus 로고
    • Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
    • J. Luu et al., "Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect," ACM FPGA Symp., 2011.
    • (2011) ACM FPGA Symp.
    • Luu, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.