Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 89-91

  Han, Kyung Joon ^a   Chan, Nigel ^a   Kim, Sungrae ^a   Leung, Ben ^a   Hecht, Volker ^a   Cronquist, Brian ^a   Shum, Danny ^b   Tilke, Armin ^b   Pescini, Laura ^c   Stiftinger, Martin ^c   Kakoschke, Ronald ^c  

^a Actel Corp   (United States)

^b Infineon Technologies Dresden GmbH and Co OHG   (United States)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; LOGIC GATES; TENSORS;

CELL SIZE; DEEP TRENCH ISOLATION; DESIGN RULES; ELECTRICAL CHARACTERISTIC; FOWLER-NORDHEIM; GATE INDUCED DRAIN LEAKAGES; PROGRAM AND ERASE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84882180564     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405688     Document Type: Conference Paper

References (6)

1. R. Lipp, R. Freeman, T. Saxe, "A High Density Flash Memory FPGA Family", IEEE 2000 Custom Integrated Circuits Conference, 2000.
2. V. Klee et al, "A 0. 13m Logic-based ASIC-compatible eDRAM technology utilizing Cu+ SiLKtm interconnect with sub-8ns random access time", IEEE 2001 IEDM Tech. Dig., pp. 407, 2001.
3. A. Tilke et al, "1/4m BiCMOS technology platform with implanted-base-or SiGe-bipolar transistor for wireless communication ICs", Solid-State Electronics, v48, 12, pp. 2243-2249, Dec. 2004.
4. D. Shum et al, "Highly Scalable Flash Memory with Novel Deep Trench Isolation Embedded into High Performance CMOS for the 90nm Node & beyond", IEEE 2005 IEDM Tech. Dig, pp. 344, 2005.
5. A. Tilke et al, "Novel Buried Bitline Integration for compact Cell Design in High-Performance embedded Flash Memory with Deep Trench Isolation, IEEE 2006 NVSM Workshop, 2006, pp. 21-23.
6. Jae-Duk Lee et al, "A New Programming Disturbance Phenomenon in NAND Flash memory by Source/Drain Hot Electrons Generated by GIDL current", IEEE NVSM Workshop 2006, pp. 31-33