A statistical gate delay model for intra-chip and inter-chip variabilities

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 31-36

  Okada, K ^a   Yamaoka, K ^a   Onodera, H ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; STATISTICS; TIME DELAY; TRANSISTORS;

GATE DELAY MODELS; INTER-CHIP VARIABILITY; INTRA-CHIP VARIABILITY; INTRA-CHIP VARIATION; RESPONSE SURFACE METHOD; SIMULATED RESULTS; STATISTICAL DELAYS; TRANSISTOR CHARACTERISTICS;

RECONFIGURABLE HARDWARE;

EID: 84954420400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1194989     Document Type: Conference Paper

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